#ifdef DRAM_LPDDR3_750M
#define LP3_DENALI_CTL_DATA_0    0x00000700 // VERSION:RD:16:16:=0x0000 DRAM_CLASS:RW:8:4:=0x07 START:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_1    0x00000000 // READ_DATA_FIFO_DEPTH:RD:24:8:=0x00 MAX_CS_REG:RD:16:2:=0x00 MAX_COL_REG:RD:8:4:=0x00 MAX_ROW_REG:RD:0:5:=0x00
#define LP3_DENALI_CTL_DATA_2    0x00000000 // MEMCD_RMODW_FIFO_DEPTH:RD:24:8:=0x00 WRITE_DATA_FIFO_PTR_WIDTH:RD:16:8:=0x00 WRITE_DATA_FIFO_DEPTH:RD:8:8:=0x00 READ_DATA_FIFO_PTR_WIDTH:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_3    0x00000000 // AXI0_RDFIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI0_CMDFIFO_LOG2_DEPTH:RD:16:8:=0x00 ASYNC_CDC_STAGES:RD:8:8:=0x00 MEMCD_RMODW_FIFO_PTR_WIDTH:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_4    0x00000000 // AXI1_CMDFIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI0_TRANS_WRFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI0_WR_ARRAY_LOG2_DEPTH:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_5    0x00000000 // AXI1_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI1_TRANS_WRFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI1_WR_ARRAY_LOG2_DEPTH:RD:8:8:=0x00 AXI1_RDFIFO_LOG2_DEPTH:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_6    0x00000000 // AXI2_TRANS_WRFIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI2_WR_ARRAY_LOG2_DEPTH:RD:16:8:=0x00 AXI2_RDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI2_CMDFIFO_LOG2_DEPTH:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_7    0x00000000 // AXI3_WR_ARRAY_LOG2_DEPTH:RD:24:8:=0x00 AXI3_RDFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI3_CMDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI2_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_8    0x00000000 // AXI4_RDFIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI4_CMDFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI3_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI3_TRANS_WRFIFO_LOG2_DEPTH:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_9    0x00000000 // AXI5_CMDFIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI4_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI4_TRANS_WRFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI4_WR_ARRAY_LOG2_DEPTH:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_10    0x00000000 // AXI5_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI5_TRANS_WRFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI5_WR_ARRAY_LOG2_DEPTH:RD:8:8:=0x00 AXI5_RDFIFO_LOG2_DEPTH:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_11    0x00001900 // TINIT:RW:8:24:=0x000019 DFS_CLOSE_BANKS:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_12    0x0000C350 // TINIT3:RW:0:24:=0x00c350
#define LP3_DENALI_CTL_DATA_13    0x000000FA // TINIT4:RW:0:24:=0x0000fa
#define LP3_DENALI_CTL_DATA_14    0x000009C4 // TINIT5:RW:0:24:=0x0009c4
#define LP3_DENALI_CTL_DATA_15    0x00000032 // TINIT_F1:RW:0:24:=0x000032
#define LP3_DENALI_CTL_DATA_16    0x000186A0 // TINIT3_F1:RW:0:24:=0x0186a0
#define LP3_DENALI_CTL_DATA_17    0x000001F4 // TINIT4_F1:RW:0:24:=0x0001f4
#define LP3_DENALI_CTL_DATA_18    0x00001388 // TINIT5_F1:RW:0:24:=0x001388
#define LP3_DENALI_CTL_DATA_19    0x0000004C // TINIT_F2:RW:0:24:=0x00004c
#define LP3_DENALI_CTL_DATA_20    0x00024A16 // TINIT3_F2:RW:0:24:=0x024a16
#define LP3_DENALI_CTL_DATA_21    0x000002EF // TINIT4_F2:RW:0:24:=0x0002ef
#define LP3_DENALI_CTL_DATA_22    0x00001D4E // TINIT5_F2:RW:0:24:=0x001d4e
#define LP3_DENALI_CTL_DATA_23    0x0000004C // TINIT_F3:RW:0:24:=0x00004c
#define LP3_DENALI_CTL_DATA_24    0x00024A16 // TINIT3_F3:RW:0:24:=0x024a16
#define LP3_DENALI_CTL_DATA_25    0x000002EF // TINIT4_F3:RW:0:24:=0x0002ef
#define LP3_DENALI_CTL_DATA_26    0x00001D4E // TINIT5_F3:RW:0:24:=0x001d4e
#define LP3_DENALI_CTL_DATA_27    0x00000019 // TINIT_F4:RW:0:24:=0x000019
#define LP3_DENALI_CTL_DATA_28    0x0000C350 // TINIT3_F4:RW:0:24:=0x00c350
#define LP3_DENALI_CTL_DATA_29    0x000000FA // TINIT4_F4:RW:0:24:=0x0000fa
#define LP3_DENALI_CTL_DATA_30    0x000009C4 // NO_AUTO_MRR_INIT:RW:24:1:=0x00 TINIT5_F4:RW:0:24:=0x0009c4
#define LP3_DENALI_CTL_DATA_31    0x00000000 // NO_MRW_INIT:RW:24:1:=0x00 NO_MRW_BT_INIT:RW:16:1:=0x00 DFI_INV_DATA_CS:RW:8:1:=0x00 MRR_ERROR_STATUS:RD:0:2:=0x00
#define LP3_DENALI_CTL_DATA_32    0x00000101 // DFIBUS_BOOT_FREQ:RW:24:3:=0x00 DFIBUS_FREQ_INIT:RW:16:3:=0x00 PHY_INDEP_TRAIN_MODE:RW:8:1:=0x01 NO_PHY_IND_TRAIN_INIT:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_33    0x03020100 // DFIBUS_FREQ_F3:RW:24:5:=0x03 DFIBUS_FREQ_F2:RW:16:5:=0x02 DFIBUS_FREQ_F1:RW:8:5:=0x01 DFIBUS_FREQ:RW:0:5:=0x00
#define LP3_DENALI_CTL_DATA_34    0x00000004 // DFIBUS_FREQ_F4:RW:0:5:=0x04
#define LP3_DENALI_CTL_DATA_35    0x00000032 // TRST_PWRON:RW:0:32:=0x00000032
#define LP3_DENALI_CTL_DATA_36    0x0000007D // CKE_INACTIVE:RW:0:32:=0x0000007d
#define LP3_DENALI_CTL_DATA_37    0x0410030C // WRLAT_F1:RW:24:7:=0x04 CASLAT_LIN_F1:RW:16:7:=0x10 WRLAT:RW:8:7:=0x03 CASLAT_LIN:RW:0:7:=0x0c
#define LP3_DENALI_CTL_DATA_38    0x06180618 // WRLAT_F3:RW:24:7:=0x06 CASLAT_LIN_F3:RW:16:7:=0x18 WRLAT_F2:RW:8:7:=0x06 CASLAT_LIN_F2:RW:0:7:=0x18
#define LP3_DENALI_CTL_DATA_39    0x0404030C // TCCD:RW:24:5:=0x04 TBST_INT_INTERVAL:RW:16:3:=0x04 WRLAT_F4:RW:8:7:=0x03 CASLAT_LIN_F4:RW:0:7:=0x0c
#define LP3_DENALI_CTL_DATA_40    0x0B100300 // TRAS_MIN:RW:24:8:=0x0b TRC:RW:16:8:=0x10 TRRD:RW:8:8:=0x03 TCCDMW:RW:0:6:=0x00
#define LP3_DENALI_CTL_DATA_41    0x010D0504 // CA_DEFAULT_VAL:RW:24:1:=0x01 TFAW:RW:16:8:=0x0d TRP:RW:8:8:=0x05 TWTR:RW:0:6:=0x04
#define LP3_DENALI_CTL_DATA_42    0x04152005 // TWTR_F1:RW:24:6:=0x04 TRAS_MIN_F1:RW:16:8:=0x15 TRC_F1:RW:8:8:=0x20 TRRD_F1:RW:0:8:=0x05
#define LP3_DENALI_CTL_DATA_43    0x08011909 // TRRD_F2:RW:24:8:=0x08 CA_DEFAULT_VAL_F1:RW:16:1:=0x01 TFAW_F1:RW:8:8:=0x19 TRP_F1:RW:0:8:=0x09
#define LP3_DENALI_CTL_DATA_44    0x0E062030 // TRP_F2:RW:24:8:=0x0e TWTR_F2:RW:16:6:=0x06 TRAS_MIN_F2:RW:8:8:=0x20 TRC_F2:RW:0:8:=0x30
#define LP3_DENALI_CTL_DATA_45    0x30080126 // TRC_F3:RW:24:8:=0x30 TRRD_F3:RW:16:8:=0x08 CA_DEFAULT_VAL_F2:RW:8:1:=0x01 TFAW_F2:RW:0:8:=0x26
#define LP3_DENALI_CTL_DATA_46    0x260E0620 // TFAW_F3:RW:24:8:=0x26 TRP_F3:RW:16:8:=0x0e TWTR_F3:RW:8:6:=0x06 TRAS_MIN_F3:RW:0:8:=0x20
#define LP3_DENALI_CTL_DATA_47    0x0B100301 // TRAS_MIN_F4:RW:24:8:=0x0b TRC_F4:RW:16:8:=0x10 TRRD_F4:RW:8:8:=0x03 CA_DEFAULT_VAL_F3:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_48    0x010D0504 // CA_DEFAULT_VAL_F4:RW:24:1:=0x01 TFAW_F4:RW:16:8:=0x0d TRP_F4:RW:8:8:=0x05 TWTR_F4:RW:0:6:=0x04
#define LP3_DENALI_CTL_DATA_49    0x000A0A04 // TMOD:RW:16:8:=0x0a TMRD:RW:8:8:=0x0a TRTP:RW:0:8:=0x04
#define LP3_DENALI_CTL_DATA_50    0x0300445C // TCKE:RW:24:4:=0x03 TRAS_MAX:RW:0:17:=0x00445c
#define LP3_DENALI_CTL_DATA_51    0x0A0A0404 // TMOD_F1:RW:24:8:=0x0a TMRD_F1:RW:16:8:=0x0a TRTP_F1:RW:8:8:=0x04 TCKESR:RW:0:8:=0x04
#define LP3_DENALI_CTL_DATA_52    0x040088B8 // TCKE_F1:RW:24:4:=0x04 TRAS_MAX_F1:RW:0:17:=0x0088b8
#define LP3_DENALI_CTL_DATA_53    0x0A0A0608 // TMOD_F2:RW:24:8:=0x0a TMRD_F2:RW:16:8:=0x0a TRTP_F2:RW:8:8:=0x06 TCKESR_F1:RW:0:8:=0x08
#define LP3_DENALI_CTL_DATA_54    0x0600CD21 // TCKE_F2:RW:24:4:=0x06 TRAS_MAX_F2:RW:0:17:=0x00cd21
#define LP3_DENALI_CTL_DATA_55    0x0A0A060C // TMOD_F3:RW:24:8:=0x0a TMRD_F3:RW:16:8:=0x0a TRTP_F3:RW:8:8:=0x06 TCKESR_F2:RW:0:8:=0x0c
#define LP3_DENALI_CTL_DATA_56    0x0600CD21 // TCKE_F3:RW:24:4:=0x06 TRAS_MAX_F3:RW:0:17:=0x00cd21
#define LP3_DENALI_CTL_DATA_57    0x0A0A040C // TMOD_F4:RW:24:8:=0x0a TMRD_F4:RW:16:8:=0x0a TRTP_F4:RW:8:8:=0x04 TCKESR_F3:RW:0:8:=0x0c
#define LP3_DENALI_CTL_DATA_58    0x0300445C // TCKE_F4:RW:24:4:=0x03 TRAS_MAX_F4:RW:0:17:=0x00445c
#define LP3_DENALI_CTL_DATA_59    0x02030004 // RESERVED:RW:24:3:=0x02 RESERVED:RW:16:3:=0x03 TPPD:RW_D:8:3:=0x00 TCKESR_F4:RW:0:8:=0x04
#define LP3_DENALI_CTL_DATA_60    0x09040500 // TRCD_F1:RW:24:8:=0x09 TWR:RW:16:6:=0x04 TRCD:RW:8:8:=0x05 WRITEINTERP:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_61    0x0E0C0E08 // TRCD_F3:RW:24:8:=0x0e TWR_F2:RW:16:6:=0x0c TRCD_F2:RW:8:8:=0x0e TWR_F1:RW:0:6:=0x08
#define LP3_DENALI_CTL_DATA_62    0x0404050C // TMRR:RW:24:4:=0x04 TWR_F4:RW:16:6:=0x04 TRCD_F4:RW:8:8:=0x05 TWR_F3:RW:0:6:=0x0c
#define LP3_DENALI_CTL_DATA_63    0x14000A0A // TCAMRD:RW:24:6:=0x14 TCAENT:RW:8:10:=0x000a TCACKEL:RW:0:5:=0x0a
#define LP3_DENALI_CTL_DATA_64    0x02010A0A // TMRZ_F1:RW:24:5:=0x02 TMRZ:RW:16:5:=0x01 TCACKEH:RW:8:5:=0x0a TCAEXT:RW:0:5:=0x0a
#define LP3_DENALI_CTL_DATA_65    0x00010303 // AP:RW:24:1:=0x00 TMRZ_F4:RW:16:5:=0x01 TMRZ_F3:RW:8:5:=0x03 TMRZ_F2:RW:0:5:=0x03
#define LP3_DENALI_CTL_DATA_66    0x110B0101 // TDAL_F1:RW:24:8:=0x11 TDAL:RW:16:8:=0x0b TRAS_LOCKOUT:RW:8:1:=0x01 CONCURRENTAP:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_67    0x030B1A1A // BSTLEN:RW_D:24:5:=0x03 TDAL_F4:RW:16:8:=0x0b TDAL_F3:RW:8:8:=0x1a TDAL_F2:RW:0:8:=0x1a
#define LP3_DENALI_CTL_DATA_68    0x10100B06 // TRP_AB_F3:RW:24:8:=0x10 TRP_AB_F2:RW:16:8:=0x10 TRP_AB_F1:RW:8:8:=0x0b TRP_AB:RW:0:8:=0x06
#define LP3_DENALI_CTL_DATA_69    0x01010006 // RESERVED:RW:24:1:=0x01 OPTIMAL_RMODW_EN:RW:16:1:=0x01 REG_DIMM_ENABLE:RW:8:1:=0x00 TRP_AB_F4:RW:0:8:=0x06
#define LP3_DENALI_CTL_DATA_70    0x01000000 // TREF_ENABLE:RW:24:1:=0x01 RESERVED:RW:16:1:=0x00 AREFRESH:WR:8:1:=0x00 NO_MEMORY_DM:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_71    0x00003503 // TRFC:RW:8:10:=0x0035 RESERVED:RW:0:3:=0x03
#define LP3_DENALI_CTL_DATA_72    0x006903C7 // TRFC_F1:RW:16:10:=0x0069 TREF:RW:0:16:=0x03c7
#define LP3_DENALI_CTL_DATA_73    0x009E0796 // TRFC_F2:RW:16:10:=0x009e TREF_F1:RW:0:16:=0x0796
#define LP3_DENALI_CTL_DATA_74    0x009E0B65 // TRFC_F3:RW:16:10:=0x009e TREF_F2:RW:0:16:=0x0b65
#define LP3_DENALI_CTL_DATA_75    0x00350B65 // TRFC_F4:RW:16:10:=0x0035 TREF_F3:RW:0:16:=0x0b65
#define LP3_DENALI_CTL_DATA_76    0x000003C7 // TREF_F4:RW:0:16:=0x03c7
#define LP3_DENALI_CTL_DATA_77    0x00040003 // TPDEX_F1:RW:16:16:=0x0004 TPDEX:RW:0:16:=0x0003
#define LP3_DENALI_CTL_DATA_78    0x00060006 // TPDEX_F3:RW:16:16:=0x0006 TPDEX_F2:RW:0:16:=0x0006
#define LP3_DENALI_CTL_DATA_79    0x00000003 // SHUTDOWN_STATUS:RD:24:6:=0x00 SHUTDOWN_MEM_GATE:RW:16:1:=0x00 TPDEX_F4:RW:0:16:=0x0003
#define LP3_DENALI_CTL_DATA_80    0x0E0E0905 // TMRRI_F3:RW:24:8:=0x0e TMRRI_F2:RW:16:8:=0x0e TMRRI_F1:RW:8:8:=0x09 TMRRI:RW:0:8:=0x05
#define LP3_DENALI_CTL_DATA_81    0x00000005 // TCKEHCS:RW:24:4:=0x00 TCKELCS:RW:16:4:=0x00 TCSCKE:RW:8:4:=0x00 TMRRI_F4:RW:0:8:=0x05
#define LP3_DENALI_CTL_DATA_82    0x00000000 // TCKELCS_F1:RW:24:4:=0x00 TCSCKE_F1:RW:16:4:=0x00 TZQCKE:RW:8:4:=0x00 TMRWCKEL:RW:0:5:=0x00
#define LP3_DENALI_CTL_DATA_83    0x00000000 // TCSCKE_F2:RW:24:4:=0x00 TZQCKE_F1:RW:16:4:=0x00 TMRWCKEL_F1:RW:8:5:=0x00 TCKEHCS_F1:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_84    0x00000000 // TZQCKE_F2:RW:24:4:=0x00 TMRWCKEL_F2:RW:16:5:=0x00 TCKEHCS_F2:RW:8:4:=0x00 TCKELCS_F2:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_85    0x00000000 // TMRWCKEL_F3:RW:24:5:=0x00 TCKEHCS_F3:RW:16:4:=0x00 TCKELCS_F3:RW:8:4:=0x00 TCSCKE_F3:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_86    0x00000000 // TCKEHCS_F4:RW:24:4:=0x00 TCKELCS_F4:RW:16:4:=0x00 TCSCKE_F4:RW:8:4:=0x00 TZQCKE_F3:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_87    0x00370000 // TXSR:RW:16:16:=0x0037 TZQCKE_F4:RW:8:4:=0x00 TMRWCKEL_F4:RW:0:5:=0x00
#define LP3_DENALI_CTL_DATA_88    0x006E0037 // TXSR_F1:RW:16:16:=0x006e TXSNR:RW:0:16:=0x0037
#define LP3_DENALI_CTL_DATA_89    0x00A6006E // TXSR_F2:RW:16:16:=0x00a6 TXSNR_F1:RW:0:16:=0x006e
#define LP3_DENALI_CTL_DATA_90    0x00A600A6 // TXSR_F3:RW:16:16:=0x00a6 TXSNR_F2:RW:0:16:=0x00a6
#define LP3_DENALI_CTL_DATA_91    0x003700A6 // TXSR_F4:RW:16:16:=0x0037 TXSNR_F3:RW:0:16:=0x00a6
#define LP3_DENALI_CTL_DATA_92    0x00000037 // TCKEHCMD:RW:24:4:=0x00 TCKELCMD:RW:16:4:=0x00 TXSNR_F4:RW:0:16:=0x0037
#define LP3_DENALI_CTL_DATA_93    0x00000000 // TCKELPD:RW:24:4:=0x00 TESCKE:RW:16:3:=0x00 TSR:RW:8:8:=0x00 TCKCKEL:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_94    0x00000000 // TCKEHCMD_F1:RW:24:4:=0x00 TCKELCMD_F1:RW:16:4:=0x00 TCMDCKE:RW:8:4:=0x00 TCSCKEH:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_95    0x00000000 // TCKELPD_F1:RW:24:4:=0x00 TESCKE_F1:RW:16:3:=0x00 TSR_F1:RW:8:8:=0x00 TCKCKEL_F1:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_96    0x00000000 // TCKEHCMD_F2:RW:24:4:=0x00 TCKELCMD_F2:RW:16:4:=0x00 TCMDCKE_F1:RW:8:4:=0x00 TCSCKEH_F1:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_97    0x00000000 // TCKELPD_F2:RW:24:4:=0x00 TESCKE_F2:RW:16:3:=0x00 TSR_F2:RW:8:8:=0x00 TCKCKEL_F2:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_98    0x00000000 // TCKEHCMD_F3:RW:24:4:=0x00 TCKELCMD_F3:RW:16:4:=0x00 TCMDCKE_F2:RW:8:4:=0x00 TCSCKEH_F2:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_99    0x00000000 // TCKELPD_F3:RW:24:4:=0x00 TESCKE_F3:RW:16:3:=0x00 TSR_F3:RW:8:8:=0x00 TCKCKEL_F3:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_100    0x00000000 // TCKEHCMD_F4:RW:24:4:=0x00 TCKELCMD_F4:RW:16:4:=0x00 TCMDCKE_F3:RW:8:4:=0x00 TCSCKEH_F3:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_101    0x00000000 // TCKELPD_F4:RW:24:4:=0x00 TESCKE_F4:RW:16:3:=0x00 TSR_F4:RW:8:8:=0x00 TCKCKEL_F4:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_102    0x00000000 // SREFRESH_EXIT_NO_REFRESH:RW:24:1:=0x00 PWRUP_SREFRESH_EXIT:RW:16:1:=0x00 TCMDCKE_F4:RW:8:4:=0x00 TCSCKEH_F4:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_103    0x00000301 // RESERVED:WR:16:9:=0x0000 CKE_DELAY:RW:8:3:=0x03 ENABLE_QUICK_SREFRESH:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_104    0x00000100 // DFS_WRLVL_EN:RW:24:1:=0x00 DFS_CALVL_EN:RW:16:1:=0x00 DFS_ZQ_EN:RW:8:1:=0x01 DFS_STATUS:RD:0:2:=0x00
#define LP3_DENALI_CTL_DATA_105    0x00000000 // DFS_PROMOTE_THRESHOLD:RW:16:16:=0x0000 DFS_RDLVL_GATE_EN:RW:8:1:=0x00 DFS_RDLVL_EN:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_106    0x00000000 // DFS_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 DFS_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_107    0x00000000 // DFS_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 DFS_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_108    0x01000000 // RESERVED:RW:24:3:=0x01 ZQ_CALINIT_CS_CL_STATUS:RD:16:2:=0x00 ZQ_CALLATCH_STATUS:RD:8:2:=0x00 ZQ_CALSTART_STATUS:RD:0:2:=0x00
#define LP3_DENALI_CTL_DATA_109    0x80104002 // RESERVED:RW:24:8:=0x80 RESERVED:RW:16:8:=0x10 RESERVED:RW:8:8:=0x40 RESERVED:RW:0:3:=0x02
#define LP3_DENALI_CTL_DATA_110    0x00040003 // UPD_CTRLUPD_HIGH_THRESHOLD:RW:16:16:=0x0004 UPD_CTRLUPD_NORM_THRESHOLD:RW:0:16:=0x0003
#define LP3_DENALI_CTL_DATA_111    0x00040005 // UPD_CTRLUPD_SW_PROMOTE_THRESHOLD:RW:16:16:=0x0004 UPD_CTRLUPD_TIMEOUT:RW:0:16:=0x0005
#define LP3_DENALI_CTL_DATA_112    0x00030000 // UPD_CTRLUPD_NORM_THRESHOLD_F1:RW:16:16:=0x0003 UPD_PHYUPD_DFI_PROMOTE_THRESHOLD:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_113    0x00050004 // UPD_CTRLUPD_TIMEOUT_F1:RW:16:16:=0x0005 UPD_CTRLUPD_HIGH_THRESHOLD_F1:RW:0:16:=0x0004
#define LP3_DENALI_CTL_DATA_114    0x00000004 // UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0004
#define LP3_DENALI_CTL_DATA_115    0x00040003 // UPD_CTRLUPD_HIGH_THRESHOLD_F2:RW:16:16:=0x0004 UPD_CTRLUPD_NORM_THRESHOLD_F2:RW:0:16:=0x0003
#define LP3_DENALI_CTL_DATA_116    0x00040005 // UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0004 UPD_CTRLUPD_TIMEOUT_F2:RW:0:16:=0x0005
#define LP3_DENALI_CTL_DATA_117    0x00030000 // UPD_CTRLUPD_NORM_THRESHOLD_F3:RW:16:16:=0x0003 UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_118    0x00050004 // UPD_CTRLUPD_TIMEOUT_F3:RW:16:16:=0x0005 UPD_CTRLUPD_HIGH_THRESHOLD_F3:RW:0:16:=0x0004
#define LP3_DENALI_CTL_DATA_119    0x00000004 // UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0004
#define LP3_DENALI_CTL_DATA_120    0x00040003 // UPD_CTRLUPD_HIGH_THRESHOLD_F4:RW:16:16:=0x0004 UPD_CTRLUPD_NORM_THRESHOLD_F4:RW:0:16:=0x0003
#define LP3_DENALI_CTL_DATA_121    0x00040005 // UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0004 UPD_CTRLUPD_TIMEOUT_F4:RW:0:16:=0x0005
#define LP3_DENALI_CTL_DATA_122    0x0F1C0000 // TDFI_PHYMSTR_MAX:RW:16:16:=0x0f1c UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_123    0x0000078E // PHYMSTR_DFI_PROMOTE_THRESHOLD:RW:16:16:=0x0000 TDFI_PHYMSTR_RESP:RW:0:16:=0x078e
#define LP3_DENALI_CTL_DATA_124    0x0F2C1E58 // TDFI_PHYMSTR_RESP_F1:RW:16:16:=0x0f2c TDFI_PHYMSTR_MAX_F1:RW:0:16:=0x1e58
#define LP3_DENALI_CTL_DATA_125    0x2D940000 // TDFI_PHYMSTR_MAX_F2:RW:16:16:=0x2d94 PHYMSTR_DFI_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_126    0x000016CA // PHYMSTR_DFI_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 TDFI_PHYMSTR_RESP_F2:RW:0:16:=0x16ca
#define LP3_DENALI_CTL_DATA_127    0x16CA2D94 // TDFI_PHYMSTR_RESP_F3:RW:16:16:=0x16ca TDFI_PHYMSTR_MAX_F3:RW:0:16:=0x2d94
#define LP3_DENALI_CTL_DATA_128    0x0F1C0000 // TDFI_PHYMSTR_MAX_F4:RW:16:16:=0x0f1c PHYMSTR_DFI_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_129    0x0000078E // PHYMSTR_DFI_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 TDFI_PHYMSTR_RESP_F4:RW:0:16:=0x078e
#define LP3_DENALI_CTL_DATA_130    0x00000000 // MRR_TEMPCHK_NORM_THRESHOLD:RW:16:16:=0x0000 PHYMSTR_ERROR_STATUS:RD:8:2:=0x00 PHYMSTR_NO_AREF:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_131    0x00000000 // MRR_TEMPCHK_TIMEOUT:RW:16:16:=0x0000 MRR_TEMPCHK_HIGH_THRESHOLD:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_132    0x00000000 // MRR_TEMPCHK_HIGH_THRESHOLD_F1:RW:16:16:=0x0000 MRR_TEMPCHK_NORM_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_133    0x00000000 // MRR_TEMPCHK_NORM_THRESHOLD_F2:RW:16:16:=0x0000 MRR_TEMPCHK_TIMEOUT_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_134    0x00000000 // MRR_TEMPCHK_TIMEOUT_F2:RW:16:16:=0x0000 MRR_TEMPCHK_HIGH_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_135    0x00000000 // MRR_TEMPCHK_HIGH_THRESHOLD_F3:RW:16:16:=0x0000 MRR_TEMPCHK_NORM_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_136    0x00000000 // MRR_TEMPCHK_NORM_THRESHOLD_F4:RW:16:16:=0x0000 MRR_TEMPCHK_TIMEOUT_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_137    0x00000000 // MRR_TEMPCHK_TIMEOUT_F4:RW:16:16:=0x0000 MRR_TEMPCHK_HIGH_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_138    0x02020200 // CKSRE_F1:RW:24:8:=0x02 CKSRX:RW:16:8:=0x02 CKSRE:RW:8:8:=0x02 LOWPOWER_REFRESH_ENABLE:RW:0:2:=0x00
#define LP3_DENALI_CTL_DATA_139    0x02020202 // CKSRE_F3:RW:24:8:=0x02 CKSRX_F2:RW:16:8:=0x02 CKSRE_F2:RW:8:8:=0x02 CKSRX_F1:RW:0:8:=0x02
#define LP3_DENALI_CTL_DATA_140    0x00020202 // CKSRX_F4:RW:16:8:=0x02 CKSRE_F4:RW:8:8:=0x02 CKSRX_F3:RW:0:8:=0x02
#define LP3_DENALI_CTL_DATA_141    0x02000000 // LPI_SR_WAKEUP:RW:24:4:=0x02 LPI_PD_WAKEUP:RW:16:4:=0x00 LP_CMD:WR:0:9:=0x0000
#define LP3_DENALI_CTL_DATA_142    0x07030203 // LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP:RW:24:4:=0x07 LPI_SRPD_DEEP_WAKEUP:RW:16:4:=0x03 LPI_SRPD_LITE_WAKEUP:RW:8:4:=0x02 LPI_SR_MCCLK_GATE_WAKEUP:RW:0:4:=0x03
#define LP3_DENALI_CTL_DATA_143    0x0200040F // LPI_SR_WAKEUP_F1:RW:24:4:=0x02 LPI_PD_WAKEUP_F1:RW:16:4:=0x00 LPI_TIMER_WAKEUP:RW:8:4:=0x04 LPI_DPD_WAKEUP:RW:0:4:=0x0f
#define LP3_DENALI_CTL_DATA_144    0x07030203 // LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F1:RW:24:4:=0x07 LPI_SRPD_DEEP_WAKEUP_F1:RW:16:4:=0x03 LPI_SRPD_LITE_WAKEUP_F1:RW:8:4:=0x02 LPI_SR_MCCLK_GATE_WAKEUP_F1:RW:0:4:=0x03
#define LP3_DENALI_CTL_DATA_145    0x0200040F // LPI_SR_WAKEUP_F2:RW:24:4:=0x02 LPI_PD_WAKEUP_F2:RW:16:4:=0x00 LPI_TIMER_WAKEUP_F1:RW:8:4:=0x04 LPI_DPD_WAKEUP_F1:RW:0:4:=0x0f
#define LP3_DENALI_CTL_DATA_146    0x07030203 // LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F2:RW:24:4:=0x07 LPI_SRPD_DEEP_WAKEUP_F2:RW:16:4:=0x03 LPI_SRPD_LITE_WAKEUP_F2:RW:8:4:=0x02 LPI_SR_MCCLK_GATE_WAKEUP_F2:RW:0:4:=0x03
#define LP3_DENALI_CTL_DATA_147    0x0200040F // LPI_SR_WAKEUP_F3:RW:24:4:=0x02 LPI_PD_WAKEUP_F3:RW:16:4:=0x00 LPI_TIMER_WAKEUP_F2:RW:8:4:=0x04 LPI_DPD_WAKEUP_F2:RW:0:4:=0x0f
#define LP3_DENALI_CTL_DATA_148    0x07030203 // LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F3:RW:24:4:=0x07 LPI_SRPD_DEEP_WAKEUP_F3:RW:16:4:=0x03 LPI_SRPD_LITE_WAKEUP_F3:RW:8:4:=0x02 LPI_SR_MCCLK_GATE_WAKEUP_F3:RW:0:4:=0x03
#define LP3_DENALI_CTL_DATA_149    0x0200040F // LPI_SR_WAKEUP_F4:RW:24:4:=0x02 LPI_PD_WAKEUP_F4:RW:16:4:=0x00 LPI_TIMER_WAKEUP_F3:RW:8:4:=0x04 LPI_DPD_WAKEUP_F3:RW:0:4:=0x0f
#define LP3_DENALI_CTL_DATA_150    0x07030203 // LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F4:RW:24:4:=0x07 LPI_SRPD_DEEP_WAKEUP_F4:RW:16:4:=0x03 LPI_SRPD_LITE_WAKEUP_F4:RW:8:4:=0x02 LPI_SR_MCCLK_GATE_WAKEUP_F4:RW:0:4:=0x03
#define LP3_DENALI_CTL_DATA_151    0x000F040F // LPI_WAKEUP_EN:RW:16:5:=0x0f LPI_TIMER_WAKEUP_F4:RW:8:4:=0x04 LPI_DPD_WAKEUP_F4:RW:0:4:=0x0f
#define LP3_DENALI_CTL_DATA_152    0x00040003 // LPI_WAKEUP_TIMEOUT:RW:16:12:=0x0004 LPI_TIMER_COUNT:RW:0:12:=0x0003
#define LP3_DENALI_CTL_DATA_153    0x00000007 // LP_AUTO_ENTRY_EN:RW:24:4:=0x00 LP_STATE_CS1:RD:16:6:=0x00 LP_STATE_CS0:RD:8:6:=0x00 TDFI_LP_RESP:RW:0:3:=0x07
#define LP3_DENALI_CTL_DATA_154    0x00000000 // LP_AUTO_PD_IDLE:RW:16:12:=0x0000 LP_AUTO_MEM_GATE_EN:RW:8:3:=0x00 LP_AUTO_EXIT_EN:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_155    0x00000000 // LP_AUTO_SR_MC_GATE_IDLE:RW:24:8:=0x00 LP_AUTO_SR_IDLE:RW:16:8:=0x00 LP_AUTO_SRPD_LITE_IDLE:RW:0:12:=0x0000
#define LP3_DENALI_CTL_DATA_156    0x00000000 // HW_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 HW_PROMOTE_THRESHOLD:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_157    0x00000000 // HW_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 HW_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_158    0x00000000 // LPC_PROMOTE_THRESHOLD:RW:16:16:=0x0000 HW_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_159    0x00000000 // LPC_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 LPC_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_160    0x00000000 // LPC_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 LPC_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_161    0x00000000 // RESERVED:RW:24:1:=0x00 LPC_SR_PHYMSTR_EN:RW:16:1:=0x00 LPC_SR_PHYUPD_EN:RW:8:1:=0x00 LPC_SR_CTRLUPD_EN:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_162    0x04040100 // PCPCS_PD_EXIT_DEPTH:RW:24:5:=0x04 PCPCS_PD_ENTER_DEPTH:RW:16:5:=0x04 PCPCS_PD_EN:RW:8:1:=0x01 LPC_SR_ZQ_EN:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_163    0x00030000 // LP_CS:RW:24:2:=0x00 PCPCS_CS_MAP:RW:16:2:=0x03 PCPCS_PD_MASK:RW:8:2:=0x00 PCPCS_PD_ENTER_TIMER:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_164    0x00000000 // CS1_IDLE:RD:8:1:=0x00 CS0_IDLE:RD:0:1:=0x00
#define LP3_DENALI_CTL_DATA_165    0x0001E848 // TDPD:RW:0:24:=0x01e848
#define LP3_DENALI_CTL_DATA_166    0x0003D090 // TDPD_F1:RW:0:24:=0x03d090
#define LP3_DENALI_CTL_DATA_167    0x0005B936 // TDPD_F2:RW:0:24:=0x05b936
#define LP3_DENALI_CTL_DATA_168    0x0005B936 // TDPD_F3:RW:0:24:=0x05b936
#define LP3_DENALI_CTL_DATA_169    0x0001E848 // TDPD_CNT_DONE_STATUS:RD:24:2:=0x00 TDPD_F4:RW:0:24:=0x01e848
#define LP3_DENALI_CTL_DATA_170    0xC0010003 // TDFI_INIT_START:RW_D:24:8:=0xc0 DFS_ENABLE:RW:16:1:=0x01 RESERVED:RW:8:8:=0x00 PWRUP_SREFRESH_EXIT_CS:RW:0:2:=0x03
#define LP3_DENALI_CTL_DATA_171    0x00C01000 // TDFI_INIT_START_F1:RW_D:16:8:=0xc0 TDFI_INIT_COMPLETE:RW_D:0:16:=0x1000
#define LP3_DENALI_CTL_DATA_172    0x00C01000 // TDFI_INIT_START_F2:RW_D:16:8:=0xc0 TDFI_INIT_COMPLETE_F1:RW_D:0:16:=0x1000
#define LP3_DENALI_CTL_DATA_173    0x00C01000 // TDFI_INIT_START_F3:RW_D:16:8:=0xc0 TDFI_INIT_COMPLETE_F2:RW_D:0:16:=0x1000
#define LP3_DENALI_CTL_DATA_174    0x00C01000 // TDFI_INIT_START_F4:RW_D:16:8:=0xc0 TDFI_INIT_COMPLETE_F3:RW_D:0:16:=0x1000
#define LP3_DENALI_CTL_DATA_175    0x01001000 // DFS_PHY_REG_WRITE_EN:RW:24:1:=0x01 CURRENT_REG_COPY:RD:16:3:=0x00 TDFI_INIT_COMPLETE_F4:RW_D:0:16:=0x1000
#define LP3_DENALI_CTL_DATA_176    0x00000C00 // DFS_PHY_REG_WRITE_ADDR:RW:0:32:=0x00000c00
#define LP3_DENALI_CTL_DATA_177    0x00000000 // DFS_PHY_REG_WRITE_DATA:RW:0:32:=0x00000000
#define LP3_DENALI_CTL_DATA_178    0x00000001 // DFS_PHY_REG_WRITE_DATA_F1:RW:0:32:=0x00000001
#define LP3_DENALI_CTL_DATA_179    0x00000002 // DFS_PHY_REG_WRITE_DATA_F2:RW:0:32:=0x00000002
#define LP3_DENALI_CTL_DATA_180    0x00000003 // DFS_PHY_REG_WRITE_DATA_F3:RW:0:32:=0x00000003
#define LP3_DENALI_CTL_DATA_181    0x00000004 // DFS_PHY_REG_WRITE_DATA_F4:RW:0:32:=0x00000004
#define LP3_DENALI_CTL_DATA_182    0x0000000E // DFS_PHY_REG_WRITE_MASK:RW:0:4:=0x0e
#define LP3_DENALI_CTL_DATA_183    0x00000000 // WRITE_MODEREG:RW+:0:27:=0x00000000
#define LP3_DENALI_CTL_DATA_184    0x00000000 // READ_MODEREG:RW+:8:17:=0x000000 MRW_STATUS:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_185    0x00000000 // PERIPHERAL_MRR_DATA:RD:0:40:=0x00000000
#define LP3_DENALI_CTL_DATA_186    0x00000000 // AUTO_TEMPCHK_VAL_0:RD:8:16:=0x0000 PERIPHERAL_MRR_DATA:RD:0:40:=0x00
#define LP3_DENALI_CTL_DATA_187    0x00000000 // DISABLE_UPDATE_TVRCG:RW:16:1:=0x00 AUTO_TEMPCHK_VAL_1:RD:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_188    0x00320000 // TVRCG_ENABLE:RW:16:10:=0x0032 MRW_DFS_UPDATE_FRC:RW:0:3:=0x00
#define LP3_DENALI_CTL_DATA_189    0x003F0019 // TFC:RW:16:10:=0x003f TVRCG_DISABLE:RW:0:10:=0x0019
#define LP3_DENALI_CTL_DATA_190    0x003F0000 // TVREF_LONG:RW:16:16:=0x003f TCKFSPX:RW:8:5:=0x00 TCKFSPE:RW:0:5:=0x00
#define LP3_DENALI_CTL_DATA_191    0x00320064 // TVRCG_DISABLE_F1:RW:16:10:=0x0032 TVRCG_ENABLE_F1:RW:0:10:=0x0064
#define LP3_DENALI_CTL_DATA_192    0x0000007D // TCKFSPX_F1:RW:24:5:=0x00 TCKFSPE_F1:RW:16:5:=0x00 TFC_F1:RW:0:10:=0x007d
#define LP3_DENALI_CTL_DATA_193    0x0097007D // TVRCG_ENABLE_F2:RW:16:10:=0x0097 TVREF_LONG_F1:RW:0:16:=0x007d
#define LP3_DENALI_CTL_DATA_194    0x00BC004C // TFC_F2:RW:16:10:=0x00bc TVRCG_DISABLE_F2:RW:0:10:=0x004c
#define LP3_DENALI_CTL_DATA_195    0x00BC0000 // TVREF_LONG_F2:RW:16:16:=0x00bc TCKFSPX_F2:RW:8:5:=0x00 TCKFSPE_F2:RW:0:5:=0x00
#define LP3_DENALI_CTL_DATA_196    0x004C0097 // TVRCG_DISABLE_F3:RW:16:10:=0x004c TVRCG_ENABLE_F3:RW:0:10:=0x0097
#define LP3_DENALI_CTL_DATA_197    0x000000BC // TCKFSPX_F3:RW:24:5:=0x00 TCKFSPE_F3:RW:16:5:=0x00 TFC_F3:RW:0:10:=0x00bc
#define LP3_DENALI_CTL_DATA_198    0x003200BC // TVRCG_ENABLE_F4:RW:16:10:=0x0032 TVREF_LONG_F3:RW:0:16:=0x00bc
#define LP3_DENALI_CTL_DATA_199    0x003F0019 // TFC_F4:RW:16:10:=0x003f TVRCG_DISABLE_F4:RW:0:10:=0x0019
#define LP3_DENALI_CTL_DATA_200    0x003F0000 // TVREF_LONG_F4:RW:16:16:=0x003f TCKFSPX_F4:RW:8:5:=0x00 TCKFSPE_F4:RW:0:5:=0x00
#define LP3_DENALI_CTL_DATA_201    0x00000000 // MRR_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 MRR_PROMOTE_THRESHOLD:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_202    0x00000000 // MRR_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 MRR_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_203    0x00000000 // MRW_PROMOTE_THRESHOLD:RW:16:16:=0x0000 MRR_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_204    0x00000000 // MRW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 MRW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_205    0x00000000 // MRW_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 MRW_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_206    0x06C30483 // MR2_DATA_F1_0:RW:24:8:=0x06 MR1_DATA_F1_0:RW:16:8:=0xc3 MR2_DATA_0:RW:8:8:=0x04 MR1_DATA_0:RW:0:8:=0x83
#define LP3_DENALI_CTL_DATA_207    0x1A431A43 // MR2_DATA_F3_0:RW:24:8:=0x1a MR1_DATA_F3_0:RW:16:8:=0x43 MR2_DATA_F2_0:RW:8:8:=0x1a MR1_DATA_F2_0:RW:0:8:=0x43
#define LP3_DENALI_CTL_DATA_208    0x01000483 // MR3_DATA_0:RW:24:8:=0x01 MRSINGLE_DATA_0:RW:16:8:=0x00 MR2_DATA_F4_0:RW:8:8:=0x04 MR1_DATA_F4_0:RW:0:8:=0x83
#define LP3_DENALI_CTL_DATA_209    0x01010101 // MR3_DATA_F4_0:RW:24:8:=0x01 MR3_DATA_F3_0:RW:16:8:=0x01 MR3_DATA_F2_0:RW:8:8:=0x01 MR3_DATA_F1_0:RW:0:8:=0x01
#define LP3_DENALI_CTL_DATA_210    0x07070700 // MR11_DATA_F2_0:RW:24:8:=0x07 MR11_DATA_F1_0:RW:16:8:=0x07 MR11_DATA_0:RW:8:8:=0x07 MR8_DATA_0:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_211    0x00000707 // MR12_DATA_F1_0:RW:24:8:=0x00 MR12_DATA_0:RW:16:8:=0x00 MR11_DATA_F4_0:RW:8:8:=0x07 MR11_DATA_F3_0:RW:0:8:=0x07
#define LP3_DENALI_CTL_DATA_212    0x00000000 // MR13_DATA_0:RW:24:8:=0x00 MR12_DATA_F4_0:RW:16:8:=0x00 MR12_DATA_F3_0:RW:8:8:=0x00 MR12_DATA_F2_0:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_213    0x00000000 // MR14_DATA_F3_0:RW:24:8:=0x00 MR14_DATA_F2_0:RW:16:8:=0x00 MR14_DATA_F1_0:RW:8:8:=0x00 MR14_DATA_0:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_214    0x00000000 // MR_FSP_DATA_VALID_F2_0:RW:24:1:=0x00 MR_FSP_DATA_VALID_F1_0:RW:16:1:=0x00 MR_FSP_DATA_VALID_0:RW:8:1:=0x00 MR14_DATA_F4_0:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_215    0x00000000 // MR17_DATA_0:RW:24:8:=0x00 MR16_DATA_0:RW:16:8:=0x00 MR_FSP_DATA_VALID_F4_0:RW:8:1:=0x00 MR_FSP_DATA_VALID_F3_0:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_216    0x00000000 // MR22_DATA_F2_0:RW:24:8:=0x00 MR22_DATA_F1_0:RW:16:8:=0x00 MR22_DATA_0:RW:8:8:=0x00 MR20_DATA_0:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_217    0x04830000 // MR2_DATA_1:RW:24:8:=0x04 MR1_DATA_1:RW:16:8:=0x83 MR22_DATA_F4_0:RW:8:8:=0x00 MR22_DATA_F3_0:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_218    0x1A4306C3 // MR2_DATA_F2_1:RW:24:8:=0x1a MR1_DATA_F2_1:RW:16:8:=0x43 MR2_DATA_F1_1:RW:8:8:=0x06 MR1_DATA_F1_1:RW:0:8:=0xc3
#define LP3_DENALI_CTL_DATA_219    0x04831A43 // MR2_DATA_F4_1:RW:24:8:=0x04 MR1_DATA_F4_1:RW:16:8:=0x83 MR2_DATA_F3_1:RW:8:8:=0x1a MR1_DATA_F3_1:RW:0:8:=0x43
#define LP3_DENALI_CTL_DATA_220    0x01010100 // MR3_DATA_F2_1:RW:24:8:=0x01 MR3_DATA_F1_1:RW:16:8:=0x01 MR3_DATA_1:RW:8:8:=0x01 MRSINGLE_DATA_1:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_221    0x07000101 // MR11_DATA_1:RW:24:8:=0x07 MR8_DATA_1:RD:16:8:=0x00 MR3_DATA_F4_1:RW:8:8:=0x01 MR3_DATA_F3_1:RW:0:8:=0x01
#define LP3_DENALI_CTL_DATA_222    0x07070707 // MR11_DATA_F4_1:RW:24:8:=0x07 MR11_DATA_F3_1:RW:16:8:=0x07 MR11_DATA_F2_1:RW:8:8:=0x07 MR11_DATA_F1_1:RW:0:8:=0x07
#define LP3_DENALI_CTL_DATA_223    0x00000000 // MR12_DATA_F3_1:RW:24:8:=0x00 MR12_DATA_F2_1:RW:16:8:=0x00 MR12_DATA_F1_1:RW:8:8:=0x00 MR12_DATA_1:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_224    0x00000000 // MR14_DATA_F1_1:RW:24:8:=0x00 MR14_DATA_1:RW:16:8:=0x00 MR13_DATA_1:RW:8:8:=0x00 MR12_DATA_F4_1:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_225    0x00000000 // MR_FSP_DATA_VALID_1:RW:24:1:=0x00 MR14_DATA_F4_1:RW:16:8:=0x00 MR14_DATA_F3_1:RW:8:8:=0x00 MR14_DATA_F2_1:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_226    0x00000000 // MR_FSP_DATA_VALID_F4_1:RW:24:1:=0x00 MR_FSP_DATA_VALID_F3_1:RW:16:1:=0x00 MR_FSP_DATA_VALID_F2_1:RW:8:1:=0x00 MR_FSP_DATA_VALID_F1_1:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_227    0x00000000 // MR22_DATA_1:RW:24:8:=0x00 MR20_DATA_1:RD:16:8:=0x00 MR17_DATA_1:RW:8:8:=0x00 MR16_DATA_1:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_228    0x00000000 // MR22_DATA_F4_1:RW:24:8:=0x00 MR22_DATA_F3_1:RW:16:8:=0x00 MR22_DATA_F2_1:RW:8:8:=0x00 MR22_DATA_F1_1:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_229    0x01000000 // FSP_PHY_UPDATE_MRW:RW:24:1:=0x01 RESERVED:RD:16:1:=0x00 RESERVED:RD:8:1:=0x00 RL3_SUPPORT_EN:RD:0:2:=0x00
#define LP3_DENALI_CTL_DATA_230    0x00000000 // FSP_WR_CURRENT:RW+:24:1:=0x00 FSP_OP_CURRENT:RW+:16:1:=0x00 FSP_STATUS:RW:8:1:=0x00 DFS_ALWAYS_WRITE_FSP:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_231    0x00000000 // FSP1_FRC:RW+:24:3:=0x00 FSP0_FRC:RW+:16:3:=0x00 FSP1_FRC_VALID:RW+:8:1:=0x00 FSP0_FRC_VALID:RW+:0:1:=0x00
#define LP3_DENALI_CTL_DATA_232    0x01000000 // BIST_DATA_CHECK:RW:24:1:=0x01 ADDR_SPACE:RW:16:6:=0x00 BIST_RESULT:RD:8:2:=0x00 BIST_GO:WR:0:1:=0x00
#define LP3_DENALI_CTL_DATA_233    0x00000001 // BIST_ADDR_CHECK:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_234    0x00000000 // BIST_START_ADDRESS:RW:0:34:=0x00000000
#define LP3_DENALI_CTL_DATA_235    0x00000000 // BIST_START_ADDRESS:RW:0:34:=0x00
#define LP3_DENALI_CTL_DATA_236    0x00000000 // BIST_DATA_MASK:RW:0:64:=0x00000000
#define LP3_DENALI_CTL_DATA_237    0x00000000 // BIST_DATA_MASK:RW:0:64:=0x00000000
#define LP3_DENALI_CTL_DATA_238    0x18151100 // AREF_MAX_DEFICIT:RW:24:5:=0x18 AREF_HIGH_THRESHOLD:RW:16:5:=0x15 AREF_NORM_THRESHOLD:RW:8:5:=0x11 LONG_COUNT_MASK:RW:0:5:=0x00
#define LP3_DENALI_CTL_DATA_239    0x0000000C // ZQ_CALSTART_NORM_THRESHOLD:RW:8:16:=0x0000 AREF_MAX_CREDIT:RW:0:5:=0x0c
#define LP3_DENALI_CTL_DATA_240    0x00000000 // ZQ_CALLATCH_HIGH_THRESHOLD:RW:16:16:=0x0000 ZQ_CALSTART_HIGH_THRESHOLD:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_241    0x00000000 // ZQ_CS_HIGH_THRESHOLD:RW:16:16:=0x0000 ZQ_CS_NORM_THRESHOLD:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_242    0x00000000 // ZQ_CALLATCH_TIMEOUT:RW:16:16:=0x0000 ZQ_CALSTART_TIMEOUT:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_243    0x00000000 // ZQ_PROMOTE_THRESHOLD:RW:16:16:=0x0000 ZQ_CS_TIMEOUT:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_244    0x00000000 // ZQ_CALSTART_HIGH_THRESHOLD_F1:RW:16:16:=0x0000 ZQ_CALSTART_NORM_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_245    0x00000000 // ZQ_CS_NORM_THRESHOLD_F1:RW:16:16:=0x0000 ZQ_CALLATCH_HIGH_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_246    0x00000000 // ZQ_CALSTART_TIMEOUT_F1:RW:16:16:=0x0000 ZQ_CS_HIGH_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_247    0x00000000 // ZQ_CS_TIMEOUT_F1:RW:16:16:=0x0000 ZQ_CALLATCH_TIMEOUT_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_248    0x00000000 // ZQ_CALSTART_NORM_THRESHOLD_F2:RW:16:16:=0x0000 ZQ_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_249    0x00000000 // ZQ_CALLATCH_HIGH_THRESHOLD_F2:RW:16:16:=0x0000 ZQ_CALSTART_HIGH_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_250    0x00000000 // ZQ_CS_HIGH_THRESHOLD_F2:RW:16:16:=0x0000 ZQ_CS_NORM_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_251    0x00000000 // ZQ_CALLATCH_TIMEOUT_F2:RW:16:16:=0x0000 ZQ_CALSTART_TIMEOUT_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_252    0x00000000 // ZQ_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 ZQ_CS_TIMEOUT_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_253    0x00000000 // ZQ_CALSTART_HIGH_THRESHOLD_F3:RW:16:16:=0x0000 ZQ_CALSTART_NORM_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_254    0x00000000 // ZQ_CS_NORM_THRESHOLD_F3:RW:16:16:=0x0000 ZQ_CALLATCH_HIGH_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_255    0x00000000 // ZQ_CALSTART_TIMEOUT_F3:RW:16:16:=0x0000 ZQ_CS_HIGH_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_256    0x00000000 // ZQ_CS_TIMEOUT_F3:RW:16:16:=0x0000 ZQ_CALLATCH_TIMEOUT_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_257    0x00000000 // ZQ_CALSTART_NORM_THRESHOLD_F4:RW:16:16:=0x0000 ZQ_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_258    0x00000000 // ZQ_CALLATCH_HIGH_THRESHOLD_F4:RW:16:16:=0x0000 ZQ_CALSTART_HIGH_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_259    0x00000000 // ZQ_CS_HIGH_THRESHOLD_F4:RW:16:16:=0x0000 ZQ_CS_NORM_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_260    0x00000000 // ZQ_CALLATCH_TIMEOUT_F4:RW:16:16:=0x0000 ZQ_CALSTART_TIMEOUT_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_261    0x00000000 // ZQ_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 ZQ_CS_TIMEOUT_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_262    0x0000FA03 // ZQINIT:RW_D:8:12:=0x00fa RESERVED:RW:0:3:=0x03
#define LP3_DENALI_CTL_DATA_263    0x0017005A // ZQCS:RW:16:12:=0x0017 ZQCL:RW:0:12:=0x005a
#define LP3_DENALI_CTL_DATA_264    0x00000000 // TZQLAT:RW:16:6:=0x00 TZQCAL:RW:0:12:=0x0000
#define LP3_DENALI_CTL_DATA_265    0x00B401F4 // ZQCL_F1:RW:16:12:=0x00b4 ZQINIT_F1:RW_D:0:12:=0x01f4
#define LP3_DENALI_CTL_DATA_266    0x0000002D // TZQCAL_F1:RW:16:12:=0x0000 ZQCS_F1:RW:0:12:=0x002d
#define LP3_DENALI_CTL_DATA_267    0x0002EF00 // ZQINIT_F2:RW_D:8:12:=0x02ef TZQLAT_F1:RW:0:6:=0x00
#define LP3_DENALI_CTL_DATA_268    0x0044010F // ZQCS_F2:RW:16:12:=0x0044 ZQCL_F2:RW:0:12:=0x010f
#define LP3_DENALI_CTL_DATA_269    0x00000000 // TZQLAT_F2:RW:16:6:=0x00 TZQCAL_F2:RW:0:12:=0x0000
#define LP3_DENALI_CTL_DATA_270    0x010F02EF // ZQCL_F3:RW:16:12:=0x010f ZQINIT_F3:RW_D:0:12:=0x02ef
#define LP3_DENALI_CTL_DATA_271    0x00000044 // TZQCAL_F3:RW:16:12:=0x0000 ZQCS_F3:RW:0:12:=0x0044
#define LP3_DENALI_CTL_DATA_272    0x0000FA00 // ZQINIT_F4:RW_D:8:12:=0x00fa TZQLAT_F3:RW:0:6:=0x00
#define LP3_DENALI_CTL_DATA_273    0x0017005A // ZQCS_F4:RW:16:12:=0x0017 ZQCL_F4:RW:0:12:=0x005a
#define LP3_DENALI_CTL_DATA_274    0x00000000 // ZQ_SW_REQ_START_LATCH_MAP:RW:24:2:=0x00 TZQLAT_F4:RW:16:6:=0x00 TZQCAL_F4:RW:0:12:=0x0000
#define LP3_DENALI_CTL_DATA_275    0x000D0000 // ZQRESET:RW:16:12:=0x000d ZQ_REQ_PENDING:RD:8:1:=0x00 ZQ_REQ:WR:0:4:=0x00
#define LP3_DENALI_CTL_DATA_276    0x00260019 // ZQRESET_F2:RW:16:12:=0x0026 ZQRESET_F1:RW:0:12:=0x0019
#define LP3_DENALI_CTL_DATA_277    0x000D0026 // ZQRESET_F4:RW:16:12:=0x000d ZQRESET_F3:RW:0:12:=0x0026
#define LP3_DENALI_CTL_DATA_278    0x01010100 // ZQ_CAL_LATCH_MAP_0:RW_D:24:2:=0x01 ZQ_CAL_START_MAP_0:RW_D:16:2:=0x01 ZQCS_ROTATE:RW:8:1:=0x01 NO_ZQ_INIT:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_279    0x01000202 // ROW_DIFF:RW:24:3:=0x01 BANK_DIFF:RW:16:2:=0x00 ZQ_CAL_LATCH_MAP_1:RW_D:8:2:=0x02 ZQ_CAL_START_MAP_1:RW_D:0:2:=0x02
#define LP3_DENALI_CTL_DATA_280    0x0A000002 // APREBIT:RW_D:24:4:=0x0a BANK_ADDR_INTLV_EN:RW:16:1:=0x00 BANK_START_BIT:RW:8:5:=0x00 COL_DIFF:RW:0:4:=0x02
#define LP3_DENALI_CTL_DATA_281    0x0101FFFF // RESERVED:RW:24:1:=0x01 ADDR_CMP_EN:RW:16:1:=0x01 COMMAND_AGE_COUNT:RW:8:8:=0xff AGE_COUNT:RW:0:8:=0xff
#define LP3_DENALI_CTL_DATA_282    0x01010101 // RW_SAME_EN:RW:24:1:=0x01 PRIORITY_EN:RW:16:1:=0x01 PLACEMENT_EN:RW:8:1:=0x01 BANK_SPLIT_EN:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_283    0x01010101 // DISABLE_RW_GROUP_W_BNK_CONFLICT:RW:24:2:=0x01 W2R_SPLIT_EN:RW:16:1:=0x01 CS_SAME_EN:RW:8:1:=0x01 RW_SAME_PAGE_EN:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_284    0x0000011B // INHIBIT_DRAM_CMD:RW:24:2:=0x00 DISABLE_RD_INTERLEAVE:RW:16:1:=0x00 SWAP_EN:RW:8:1:=0x01 NUM_Q_ENTRIES_ACT_DISABLE:RW:0:5:=0x1b
#define LP3_DENALI_CTL_DATA_285    0x01000003 // RESERVED:RW:24:4:=0x01 MEMDATA_RATIO_0:RW:16:3:=0x00 REDUC:RW:8:1:=0x00 CS_MAP:RW:0:2:=0x03
#define LP3_DENALI_CTL_DATA_286    0x00000000 // MEMDATA_RATIO_1:RW:24:3:=0x00 RESERVED:RW:16:4:=0x00 RESERVED:RW:8:4:=0x00 RESERVED:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_287    0x00000001 // RESERVED:RW:24:4:=0x00 RESERVED:RW:16:4:=0x00 RESERVED:RW:8:4:=0x00 RESERVED:RW:0:4:=0x01
#define LP3_DENALI_CTL_DATA_288    0x00000000 // CONTROLLER_BUSY:RD:24:1:=0x00 WR_ORDER_REQ:RW:16:2:=0x00 IN_ORDER_ACCEPT:RW:8:1:=0x00 Q_FULLNESS:RW:0:5:=0x00
#define LP3_DENALI_CTL_DATA_289    0x01000100 // RD_PREAMBLE_TRAINING_EN:RW:24:1:=0x01 PREAMBLE_SUPPORT:RW:16:2:=0x00 CTRLUPD_REQ_PER_AREF_EN:RW:8:1:=0x01 CTRLUPD_REQ:WR:0:1:=0x00
#define LP3_DENALI_CTL_DATA_290    0x00000000 // DFI_ERROR:RD:16:5:=0x00 RD_DBI_EN:RW:8:1:=0x00 WR_DBI_EN:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_291    0x00000000 // RESERVED:RW+:24:1:=0x00 DFI_ERROR_INFO:RD:0:20:=0x000000
#define LP3_DENALI_CTL_DATA_292    0x00000000 // INT_STATUS:RD:0:39:=0x00000000
#define LP3_DENALI_CTL_DATA_293    0x00000000 // INT_STATUS:RD:0:39:=0x00
#define LP3_DENALI_CTL_DATA_294    0x00000000 // INT_ACK:WR:0:38:=0x00000000
#define LP3_DENALI_CTL_DATA_295    0x00000000 // INT_ACK:WR:0:38:=0x00
#define LP3_DENALI_CTL_DATA_296    0x00000000 // INT_MASK:RW:0:39:=0x00000000
#define LP3_DENALI_CTL_DATA_297    0x00000000 // INT_MASK:RW:0:39:=0x00
#define LP3_DENALI_CTL_DATA_298    0x00000000 // OUT_OF_RANGE_ADDR:RD:0:34:=0x00000000
#define LP3_DENALI_CTL_DATA_299    0x00000000 // OUT_OF_RANGE_TYPE:RD:24:7:=0x00 OUT_OF_RANGE_LENGTH:RD:8:12:=0x0000 OUT_OF_RANGE_ADDR:RD:0:34:=0x00
#define LP3_DENALI_CTL_DATA_300    0x00000000 // OUT_OF_RANGE_SOURCE_ID:RD:0:19:=0x000000
#define LP3_DENALI_CTL_DATA_301    0x00000000 // BIST_EXP_DATA:RD:0:128:=0x00000000
#define LP3_DENALI_CTL_DATA_302    0x00000000 // BIST_EXP_DATA:RD:0:128:=0x00000000
#define LP3_DENALI_CTL_DATA_303    0x00000000 // BIST_EXP_DATA:RD:0:128:=0x00000000
#define LP3_DENALI_CTL_DATA_304    0x00000000 // BIST_EXP_DATA:RD:0:128:=0x00000000
#define LP3_DENALI_CTL_DATA_305    0x00000000 // BIST_FAIL_DATA:RD:0:128:=0x00000000
#define LP3_DENALI_CTL_DATA_306    0x00000000 // BIST_FAIL_DATA:RD:0:128:=0x00000000
#define LP3_DENALI_CTL_DATA_307    0x00000000 // BIST_FAIL_DATA:RD:0:128:=0x00000000
#define LP3_DENALI_CTL_DATA_308    0x00000000 // BIST_FAIL_DATA:RD:0:128:=0x00000000
#define LP3_DENALI_CTL_DATA_309    0x00000000 // BIST_FAIL_ADDR:RD:0:34:=0x00000000
#define LP3_DENALI_CTL_DATA_310    0x00000000 // BIST_FAIL_ADDR:RD:0:34:=0x00
#define LP3_DENALI_CTL_DATA_311    0x00000000 // PORT_CMD_ERROR_ADDR:RD:0:34:=0x00000000
#define LP3_DENALI_CTL_DATA_312    0x00000000 // PORT_CMD_ERROR_ID:RD:8:19:=0x000000 PORT_CMD_ERROR_ADDR:RD:0:34:=0x00
#define LP3_DENALI_CTL_DATA_313    0x02010100 // ODT_RD_MAP_CS1:RW:24:2:=0x02 ODT_WR_MAP_CS0:RW:16:2:=0x01 ODT_RD_MAP_CS0:RW:8:2:=0x01 PORT_CMD_ERROR_TYPE:RD:0:2:=0x00
#define LP3_DENALI_CTL_DATA_314    0x03020102 // TODTL_2CMD_F2:RW:24:8:=0x03 TODTL_2CMD_F1:RW:16:8:=0x02 TODTL_2CMD:RW:8:8:=0x01 ODT_WR_MAP_CS1:RW:0:2:=0x02
#define LP3_DENALI_CTL_DATA_315    0x07070103 // TODTH_RD:RW:24:4:=0x07 TODTH_WR:RW:16:4:=0x07 TODTL_2CMD_F4:RW:8:8:=0x01 TODTL_2CMD_F3:RW:0:8:=0x03
#define LP3_DENALI_CTL_DATA_316    0x01010101 // ODT_EN_F3:RW:24:1:=0x01 ODT_EN_F2:RW:16:1:=0x01 ODT_EN_F1:RW:8:1:=0x01 ODT_EN:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_317    0x02020101 // WR_TO_ODTH_F1:RW:24:6:=0x02 WR_TO_ODTH:RW:16:6:=0x02 EN_ODT_ASSERT_EXCEPT_RD:RW:8:1:=0x01 ODT_EN_F4:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_318    0x05020303 // RD_TO_ODTH:RW:24:6:=0x05 WR_TO_ODTH_F4:RW:16:6:=0x02 WR_TO_ODTH_F3:RW:8:6:=0x03 WR_TO_ODTH_F2:RW:0:6:=0x03
#define LP3_DENALI_CTL_DATA_319    0x050A0A07 // RD_TO_ODTH_F4:RW:24:6:=0x05 RD_TO_ODTH_F3:RW:16:6:=0x0a RD_TO_ODTH_F2:RW:8:6:=0x0a RD_TO_ODTH_F1:RW:0:6:=0x07
#define LP3_DENALI_CTL_DATA_320    0x08080808 // RW2MRW_DLY_F3:RW_D:24:4:=0x08 RW2MRW_DLY_F2:RW_D:16:4:=0x08 RW2MRW_DLY_F1:RW_D:8:4:=0x08 RW2MRW_DLY:RW_D:0:4:=0x08
#define LP3_DENALI_CTL_DATA_321    0x02020208 // W2R_DIFFCS_DLY:RW_D:24:5:=0x02 R2W_DIFFCS_DLY:RW_D:16:5:=0x02 R2R_DIFFCS_DLY:RW_D:8:5:=0x02 RW2MRW_DLY_F4:RW_D:0:4:=0x08
#define LP3_DENALI_CTL_DATA_322    0x01020201 // W2R_DIFFCS_DLY_F1:RW_D:24:5:=0x01 R2W_DIFFCS_DLY_F1:RW_D:16:5:=0x02 R2R_DIFFCS_DLY_F1:RW_D:8:5:=0x02 W2W_DIFFCS_DLY:RW_D:0:5:=0x01
#define LP3_DENALI_CTL_DATA_323    0x01030201 // W2R_DIFFCS_DLY_F2:RW_D:24:5:=0x01 R2W_DIFFCS_DLY_F2:RW_D:16:5:=0x03 R2R_DIFFCS_DLY_F2:RW_D:8:5:=0x02 W2W_DIFFCS_DLY_F1:RW_D:0:5:=0x01
#define LP3_DENALI_CTL_DATA_324    0x01030201 // W2R_DIFFCS_DLY_F3:RW_D:24:5:=0x01 R2W_DIFFCS_DLY_F3:RW_D:16:5:=0x03 R2R_DIFFCS_DLY_F3:RW_D:8:5:=0x02 W2W_DIFFCS_DLY_F2:RW_D:0:5:=0x01
#define LP3_DENALI_CTL_DATA_325    0x02020201 // W2R_DIFFCS_DLY_F4:RW_D:24:5:=0x02 R2W_DIFFCS_DLY_F4:RW_D:16:5:=0x02 R2R_DIFFCS_DLY_F4:RW_D:8:5:=0x02 W2W_DIFFCS_DLY_F3:RW_D:0:5:=0x01
#define LP3_DENALI_CTL_DATA_326    0x02020001 // R2W_SAMECS_DLY_F1:RW_D:24:5:=0x02 R2W_SAMECS_DLY:RW_D:16:5:=0x02 R2R_SAMECS_DLY:RW:8:5:=0x00 W2W_DIFFCS_DLY_F4:RW_D:0:5:=0x01
#define LP3_DENALI_CTL_DATA_327    0x00020202 // W2R_SAMECS_DLY:RW:24:5:=0x00 R2W_SAMECS_DLY_F4:RW_D:16:5:=0x02 R2W_SAMECS_DLY_F3:RW_D:8:5:=0x02 R2W_SAMECS_DLY_F2:RW_D:0:5:=0x02
#define LP3_DENALI_CTL_DATA_328    0x03010200 // TDQSCK_MAX_F1:RW:24:4:=0x03 TDQSCK_MIN:RW:16:2:=0x01 TDQSCK_MAX:RW:8:4:=0x02 W2W_SAMECS_DLY:RW:0:5:=0x00
#define LP3_DENALI_CTL_DATA_329    0x05020502 // TDQSCK_MAX_F3:RW:24:4:=0x05 TDQSCK_MIN_F2:RW:16:2:=0x02 TDQSCK_MAX_F2:RW:8:4:=0x05 TDQSCK_MIN_F1:RW:0:2:=0x02
#define LP3_DENALI_CTL_DATA_330    0x00010202 // SW_LEVELING_MODE:RW:24:3:=0x00 TDQSCK_MIN_F4:RW:16:2:=0x01 TDQSCK_MAX_F4:RW:8:4:=0x02 TDQSCK_MIN_F3:RW:0:2:=0x02
#define LP3_DENALI_CTL_DATA_331    0x00000000 // SWLVL_OP_DONE:RD:24:1:=0x00 SWLVL_EXIT:WR:16:1:=0x00 SWLVL_START:WR:8:1:=0x00 SWLVL_LOAD:WR:0:1:=0x00
#define LP3_DENALI_CTL_DATA_332    0x00000000 // SWLVL_RESP_3:RD:24:1:=0x00 SWLVL_RESP_2:RD:16:1:=0x00 SWLVL_RESP_1:RD:8:1:=0x00 SWLVL_RESP_0:RD:0:1:=0x00
#define LP3_DENALI_CTL_DATA_333    0x0D000001 // WLDQSEN:RW:24:6:=0x0d WRLVL_CS:RW:16:1:=0x00 WRLVL_REQ:WR:8:1:=0x00 PHYUPD_APPEND_EN:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_334    0x00010028 // WRLVL_PERIODIC:RW:24:1:=0x00 DFI_PHY_WRLVL_MODE:RW:16:1:=0x01 WRLVL_EN:RW:8:1:=0x00 WLMRD:RW:0:6:=0x28
#define LP3_DENALI_CTL_DATA_335    0x00010000 // WRLVL_ROTATE:RW:24:1:=0x00 WRLVL_AREF_EN:RW:16:1:=0x01 WRLVL_RESP_MASK:RW:8:4:=0x00 WRLVL_ON_SREF_EXIT:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_336    0x00000003 // WRLVL_NORM_THRESHOLD:RW:16:16:=0x0000 WRLVL_ERROR_STATUS:RD:8:2:=0x00 WRLVL_CS_MAP:RW:0:2:=0x03
#define LP3_DENALI_CTL_DATA_337    0x00000000 // WRLVL_TIMEOUT:RW:16:16:=0x0000 WRLVL_HIGH_THRESHOLD:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_338    0x00000000 // WRLVL_DFI_PROMOTE_THRESHOLD:RW:16:16:=0x0000 WRLVL_SW_PROMOTE_THRESHOLD:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_339    0x00000000 // WRLVL_HIGH_THRESHOLD_F1:RW:16:16:=0x0000 WRLVL_NORM_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_340    0x00000000 // WRLVL_SW_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 WRLVL_TIMEOUT_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_341    0x00000000 // WRLVL_NORM_THRESHOLD_F2:RW:16:16:=0x0000 WRLVL_DFI_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_342    0x00000000 // WRLVL_TIMEOUT_F2:RW:16:16:=0x0000 WRLVL_HIGH_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_343    0x00000000 // WRLVL_DFI_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 WRLVL_SW_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_344    0x00000000 // WRLVL_HIGH_THRESHOLD_F3:RW:16:16:=0x0000 WRLVL_NORM_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_345    0x00000000 // WRLVL_SW_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 WRLVL_TIMEOUT_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_346    0x00000000 // WRLVL_NORM_THRESHOLD_F4:RW:16:16:=0x0000 WRLVL_DFI_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_347    0x00000000 // WRLVL_TIMEOUT_F4:RW:16:16:=0x0000 WRLVL_HIGH_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_348    0x00000000 // WRLVL_DFI_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 WRLVL_SW_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_349    0x00000000 // RDLVL_SEQ_EN:RW:24:4:=0x00 RDLVL_CS:RW:16:1:=0x00 RDLVL_GATE_REQ:WR:8:1:=0x00 RDLVL_REQ:WR:0:1:=0x00
#define LP3_DENALI_CTL_DATA_350    0x00010100 // RDLVL_PERIODIC:RW:24:1:=0x00 DFI_PHY_RDLVL_GATE_MODE:RW:16:1:=0x01 DFI_PHY_RDLVL_MODE:RW:8:1:=0x01 RDLVL_GATE_SEQ_EN:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_351    0x01000000 // RDLVL_AREF_EN:RW:24:1:=0x01 RDLVL_GATE_ON_SREF_EXIT:RW:16:1:=0x00 RDLVL_GATE_PERIODIC:RW:8:1:=0x00 RDLVL_ON_SREF_EXIT:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_352    0x00000001 // RDLVL_GATE_ROTATE:RW:24:1:=0x00 RDLVL_ROTATE:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RDLVL_GATE_AREF_EN:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_353    0x00000303 // RDLVL_NORM_THRESHOLD:RW:16:16:=0x0000 RDLVL_GATE_CS_MAP:RW:8:2:=0x03 RDLVL_CS_MAP:RW:0:2:=0x03
#define LP3_DENALI_CTL_DATA_354    0x00000000 // RDLVL_TIMEOUT:RW:16:16:=0x0000 RDLVL_HIGH_THRESHOLD:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_355    0x00000000 // RDLVL_DFI_PROMOTE_THRESHOLD:RW:16:16:=0x0000 RDLVL_SW_PROMOTE_THRESHOLD:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_356    0x00000000 // RDLVL_GATE_HIGH_THRESHOLD:RW:16:16:=0x0000 RDLVL_GATE_NORM_THRESHOLD:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_357    0x00000000 // RDLVL_GATE_SW_PROMOTE_THRESHOLD:RW:16:16:=0x0000 RDLVL_GATE_TIMEOUT:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_358    0x00000000 // RDLVL_NORM_THRESHOLD_F1:RW:16:16:=0x0000 RDLVL_GATE_DFI_PROMOTE_THRESHOLD:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_359    0x00000000 // RDLVL_TIMEOUT_F1:RW:16:16:=0x0000 RDLVL_HIGH_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_360    0x00000000 // RDLVL_DFI_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 RDLVL_SW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_361    0x00000000 // RDLVL_GATE_HIGH_THRESHOLD_F1:RW:16:16:=0x0000 RDLVL_GATE_NORM_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_362    0x00000000 // RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 RDLVL_GATE_TIMEOUT_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_363    0x00000000 // RDLVL_NORM_THRESHOLD_F2:RW:16:16:=0x0000 RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_364    0x00000000 // RDLVL_TIMEOUT_F2:RW:16:16:=0x0000 RDLVL_HIGH_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_365    0x00000000 // RDLVL_DFI_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 RDLVL_SW_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_366    0x00000000 // RDLVL_GATE_HIGH_THRESHOLD_F2:RW:16:16:=0x0000 RDLVL_GATE_NORM_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_367    0x00000000 // RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 RDLVL_GATE_TIMEOUT_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_368    0x00000000 // RDLVL_NORM_THRESHOLD_F3:RW:16:16:=0x0000 RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_369    0x00000000 // RDLVL_TIMEOUT_F3:RW:16:16:=0x0000 RDLVL_HIGH_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_370    0x00000000 // RDLVL_DFI_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 RDLVL_SW_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_371    0x00000000 // RDLVL_GATE_HIGH_THRESHOLD_F3:RW:16:16:=0x0000 RDLVL_GATE_NORM_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_372    0x00000000 // RDLVL_GATE_SW_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 RDLVL_GATE_TIMEOUT_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_373    0x00000000 // RDLVL_NORM_THRESHOLD_F4:RW:16:16:=0x0000 RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_374    0x00000000 // RDLVL_TIMEOUT_F4:RW:16:16:=0x0000 RDLVL_HIGH_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_375    0x00000000 // RDLVL_DFI_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 RDLVL_SW_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_376    0x00000000 // RDLVL_GATE_HIGH_THRESHOLD_F4:RW:16:16:=0x0000 RDLVL_GATE_NORM_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_377    0x00000000 // RDLVL_GATE_SW_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 RDLVL_GATE_TIMEOUT_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_378    0x00000000 // CALVL_CS:RW:24:1:=0x00 CALVL_REQ:WR:16:1:=0x00 RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_379    0x000556AA // CALVL_PAT_0:RW:0:20:=0x0556aa
#define LP3_DENALI_CTL_DATA_380    0x000AAAAA // CALVL_BG_PAT_0:RW:0:20:=0x0aaaaa
#define LP3_DENALI_CTL_DATA_381    0x000AA955 // CALVL_PAT_1:RW:0:20:=0x0aa955
#define LP3_DENALI_CTL_DATA_382    0x00055555 // CALVL_BG_PAT_1:RW:0:20:=0x055555
#define LP3_DENALI_CTL_DATA_383    0x000B3133 // CALVL_PAT_2:RW:0:20:=0x0b3133
#define LP3_DENALI_CTL_DATA_384    0x0004CD33 // CALVL_BG_PAT_2:RW:0:20:=0x04cd33
#define LP3_DENALI_CTL_DATA_385    0x0004CECC // CALVL_PAT_3:RW:0:20:=0x04cecc
#define LP3_DENALI_CTL_DATA_386    0x000B32CC // RESERVED:RW:24:1:=0x00 CALVL_BG_PAT_3:RW:0:20:=0x0b32cc
#define LP3_DENALI_CTL_DATA_387    0x00010300 // CALVL_PERIODIC:RW:24:1:=0x00 DFI_PHY_CALVL_MODE:RW:16:1:=0x01 CALVL_SEQ_EN:RW:8:2:=0x03 RESERVED:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_388    0x03000100 // CALVL_CS_MAP:RW:24:2:=0x03 CALVL_ROTATE:RW:16:1:=0x00 CALVL_AREF_EN:RW:8:1:=0x01 CALVL_ON_SREF_EXIT:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_389    0x00000000 // CALVL_HIGH_THRESHOLD:RW:16:16:=0x0000 CALVL_NORM_THRESHOLD:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_390    0x00000000 // CALVL_SW_PROMOTE_THRESHOLD:RW:16:16:=0x0000 CALVL_TIMEOUT:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_391    0x00000000 // CALVL_NORM_THRESHOLD_F1:RW:16:16:=0x0000 CALVL_DFI_PROMOTE_THRESHOLD:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_392    0x00000000 // CALVL_TIMEOUT_F1:RW:16:16:=0x0000 CALVL_HIGH_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_393    0x00000000 // CALVL_DFI_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 CALVL_SW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_394    0x00000000 // CALVL_HIGH_THRESHOLD_F2:RW:16:16:=0x0000 CALVL_NORM_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_395    0x00000000 // CALVL_SW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 CALVL_TIMEOUT_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_396    0x00000000 // CALVL_NORM_THRESHOLD_F3:RW:16:16:=0x0000 CALVL_DFI_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_397    0x00000000 // CALVL_TIMEOUT_F3:RW:16:16:=0x0000 CALVL_HIGH_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_398    0x00000000 // CALVL_DFI_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 CALVL_SW_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_399    0x00000000 // CALVL_HIGH_THRESHOLD_F4:RW:16:16:=0x0000 CALVL_NORM_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_400    0x00000000 // CALVL_SW_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 CALVL_TIMEOUT_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_401    0x00000000 // AXI0_FIXED_PORT_PRIORITY_ENABLE:RW:24:1:=0x00 AXI0_ALL_STROBES_USED_ENABLE:RW:16:1:=0x00 CALVL_DFI_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_402    0x00000303 // AXI1_ALL_STROBES_USED_ENABLE:RW:24:1:=0x00 AXI0_FIFO_TYPE_REG:RW:16:2:=0x00 AXI0_W_PRIORITY:RW:8:4:=0x03 AXI0_R_PRIORITY:RW:0:4:=0x03
#define LP3_DENALI_CTL_DATA_403    0x00030300 // AXI1_FIFO_TYPE_REG:RW:24:2:=0x00 AXI1_W_PRIORITY:RW:16:4:=0x03 AXI1_R_PRIORITY:RW:8:4:=0x03 AXI1_FIXED_PORT_PRIORITY_ENABLE:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_404    0x03030000 // AXI2_W_PRIORITY:RW:24:4:=0x03 AXI2_R_PRIORITY:RW:16:4:=0x03 AXI2_FIXED_PORT_PRIORITY_ENABLE:RW:8:1:=0x00 AXI2_ALL_STROBES_USED_ENABLE:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_405    0x03000000 // AXI3_R_PRIORITY:RW:24:4:=0x03 AXI3_FIXED_PORT_PRIORITY_ENABLE:RW:16:1:=0x00 AXI3_ALL_STROBES_USED_ENABLE:RW:8:1:=0x00 AXI2_FIFO_TYPE_REG:RW:0:2:=0x00
#define LP3_DENALI_CTL_DATA_406    0x00000003 // AXI4_FIXED_PORT_PRIORITY_ENABLE:RW:24:1:=0x00 AXI4_ALL_STROBES_USED_ENABLE:RW:16:1:=0x00 AXI3_FIFO_TYPE_REG:RW:8:2:=0x00 AXI3_W_PRIORITY:RW:0:4:=0x03
#define LP3_DENALI_CTL_DATA_407    0x00000303 // AXI5_ALL_STROBES_USED_ENABLE:RW:24:1:=0x00 AXI4_FIFO_TYPE_REG:RW:16:2:=0x00 AXI4_W_PRIORITY:RW:8:4:=0x03 AXI4_R_PRIORITY:RW:0:4:=0x03
#define LP3_DENALI_CTL_DATA_408    0x00030300 // AXI5_FIFO_TYPE_REG:RW:24:2:=0x00 AXI5_W_PRIORITY:RW:16:4:=0x03 AXI5_R_PRIORITY:RW:8:4:=0x03 AXI5_FIXED_PORT_PRIORITY_ENABLE:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_409    0x0001210F // AXI0_CURRENT_BDW:RD:24:7:=0x00 AXI0_BDW_OVFLOW:RW:16:1:=0x01 AXI0_BDW:RW:8:7:=0x21 ARB_CMD_Q_THRESHOLD:RW:0:5:=0x0f
#define LP3_DENALI_CTL_DATA_410    0x21000121 // AXI2_BDW:RW:24:7:=0x21 AXI1_CURRENT_BDW:RD:16:7:=0x00 AXI1_BDW_OVFLOW:RW:8:1:=0x01 AXI1_BDW:RW:0:7:=0x21
#define LP3_DENALI_CTL_DATA_411    0x01210001 // AXI3_BDW_OVFLOW:RW:24:1:=0x01 AXI3_BDW:RW:16:7:=0x21 AXI2_CURRENT_BDW:RD:8:7:=0x00 AXI2_BDW_OVFLOW:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_412    0x00012100 // AXI4_CURRENT_BDW:RD:24:7:=0x00 AXI4_BDW_OVFLOW:RW:16:1:=0x01 AXI4_BDW:RW:8:7:=0x21 AXI3_CURRENT_BDW:RD:0:7:=0x00
#define LP3_DENALI_CTL_DATA_413    0x00000121 // CKE_STATUS:RD:24:2:=0x00 AXI5_CURRENT_BDW:RD:16:7:=0x00 AXI5_BDW_OVFLOW:RW:8:1:=0x01 AXI5_BDW:RW:0:7:=0x21
#define LP3_DENALI_CTL_DATA_414    0x00000000 // DLL_RST_ADJ_DLY:RW:24:8:=0x00 DLL_RST_DELAY:RW:8:16:=0x0000 MEM_RST_VALID:RD:0:1:=0x00
#define LP3_DENALI_CTL_DATA_415    0x1C170000 // TDFI_PHY_RDLAT_F1:RW_D:24:7:=0x1c TDFI_PHY_RDLAT:RW_D:16:7:=0x17 UPDATE_ERROR_STATUS:RD:8:7:=0x00 TDFI_PHY_WRLAT:RD:0:7:=0x00
#define LP3_DENALI_CTL_DATA_416    0x00172222 // TDFI_RDDATA_EN:RD:24:7:=0x00 TDFI_PHY_RDLAT_F4:RW_D:16:7:=0x17 TDFI_PHY_RDLAT_F3:RW_D:8:7:=0x22 TDFI_PHY_RDLAT_F2:RW_D:0:7:=0x22
#define LP3_DENALI_CTL_DATA_417    0x078E0800 // TDFI_CTRLUPD_MAX:RW:16:16:=0x078e TDFI_CTRLUPD_MIN:RW:8:4:=0x08 DRAM_CLK_DISABLE:RW:0:2:=0x00
#define LP3_DENALI_CTL_DATA_418    0x00000200 // TDFI_PHYUPD_TYPE0:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_419    0x00000200 // TDFI_PHYUPD_TYPE1:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_420    0x00000200 // TDFI_PHYUPD_TYPE2:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_421    0x00000200 // TDFI_PHYUPD_TYPE3:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_422    0x0000078E // TDFI_PHYUPD_RESP:RW:0:16:=0x078e
#define LP3_DENALI_CTL_DATA_423    0x00004B8C // TDFI_CTRLUPD_INTERVAL:RW:0:32:=0x00004b8c
#define LP3_DENALI_CTL_DATA_424    0x0F2C0205 // TDFI_CTRLUPD_MAX_F1:RW:16:16:=0x0f2c WRLAT_ADJ:RW:8:7:=0x02 RDLAT_ADJ:RW:0:7:=0x05
#define LP3_DENALI_CTL_DATA_425    0x00000200 // TDFI_PHYUPD_TYPE0_F1:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_426    0x00000200 // TDFI_PHYUPD_TYPE1_F1:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_427    0x00000200 // TDFI_PHYUPD_TYPE2_F1:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_428    0x00000200 // TDFI_PHYUPD_TYPE3_F1:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_429    0x00000F2C // TDFI_PHYUPD_RESP_F1:RW:0:16:=0x0f2c
#define LP3_DENALI_CTL_DATA_430    0x000097B8 // TDFI_CTRLUPD_INTERVAL_F1:RW:0:32:=0x000097b8
#define LP3_DENALI_CTL_DATA_431    0x16CA0305 // TDFI_CTRLUPD_MAX_F2:RW:16:16:=0x16ca WRLAT_ADJ_F1:RW:8:7:=0x03 RDLAT_ADJ_F1:RW:0:7:=0x05
#define LP3_DENALI_CTL_DATA_432    0x00000200 // TDFI_PHYUPD_TYPE0_F2:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_433    0x00000200 // TDFI_PHYUPD_TYPE1_F2:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_434    0x00000200 // TDFI_PHYUPD_TYPE2_F2:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_435    0x00000200 // TDFI_PHYUPD_TYPE3_F2:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_436    0x000016CA // TDFI_PHYUPD_RESP_F2:RW:0:16:=0x16ca
#define LP3_DENALI_CTL_DATA_437    0x0000E3E4 // TDFI_CTRLUPD_INTERVAL_F2:RW:0:32:=0x0000e3e4
#define LP3_DENALI_CTL_DATA_438    0x16CA0507 // TDFI_CTRLUPD_MAX_F3:RW:16:16:=0x16ca WRLAT_ADJ_F2:RW:8:7:=0x05 RDLAT_ADJ_F2:RW:0:7:=0x07
#define LP3_DENALI_CTL_DATA_439    0x00000200 // TDFI_PHYUPD_TYPE0_F3:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_440    0x00000200 // TDFI_PHYUPD_TYPE1_F3:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_441    0x00000200 // TDFI_PHYUPD_TYPE2_F3:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_442    0x00000200 // TDFI_PHYUPD_TYPE3_F3:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_443    0x000016CA // TDFI_PHYUPD_RESP_F3:RW:0:16:=0x16ca
#define LP3_DENALI_CTL_DATA_444    0x0000E3E4 // TDFI_CTRLUPD_INTERVAL_F3:RW:0:32:=0x0000e3e4
#define LP3_DENALI_CTL_DATA_445    0x078E0507 // TDFI_CTRLUPD_MAX_F4:RW:16:16:=0x078e WRLAT_ADJ_F3:RW:8:7:=0x05 RDLAT_ADJ_F3:RW:0:7:=0x07
#define LP3_DENALI_CTL_DATA_446    0x00000200 // TDFI_PHYUPD_TYPE0_F4:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_447    0x00000200 // TDFI_PHYUPD_TYPE1_F4:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_448    0x00000200 // TDFI_PHYUPD_TYPE2_F4:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_449    0x00000200 // TDFI_PHYUPD_TYPE3_F4:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_450    0x0000078E // TDFI_PHYUPD_RESP_F4:RW:0:16:=0x078e
#define LP3_DENALI_CTL_DATA_451    0x00004B8C // TDFI_CTRLUPD_INTERVAL_F4:RW:0:32:=0x00004b8c
#define LP3_DENALI_CTL_DATA_452    0x02020205 // TDFI_CTRL_DELAY_F1:RW_D:24:4:=0x02 TDFI_CTRL_DELAY:RW_D:16:4:=0x02 WRLAT_ADJ_F4:RW:8:7:=0x02 RDLAT_ADJ_F4:RW:0:7:=0x05
#define LP3_DENALI_CTL_DATA_453    0x02020202 // TDFI_DRAM_CLK_DISABLE:RW:24:4:=0x02 TDFI_CTRL_DELAY_F4:RW_D:16:4:=0x02 TDFI_CTRL_DELAY_F3:RW_D:8:4:=0x02 TDFI_CTRL_DELAY_F2:RW_D:0:4:=0x02
#define LP3_DENALI_CTL_DATA_454    0x00180303 // TDFI_WRLVL_WW:RW:16:10:=0x0018 TDFI_WRLVL_EN:RW:8:8:=0x03 TDFI_DRAM_CLK_ENABLE:RW:0:4:=0x03
#define LP3_DENALI_CTL_DATA_455    0x00000000 // TDFI_WRLVL_RESP:RW:0:32:=0x00000000
#define LP3_DENALI_CTL_DATA_456    0x00000000 // TDFI_WRLVL_MAX:RW:0:32:=0x00000000
#define LP3_DENALI_CTL_DATA_457    0x00001403 // TDFI_RDLVL_RR:RW:8:10:=0x0014 TDFI_RDLVL_EN:RW:0:8:=0x03
#define LP3_DENALI_CTL_DATA_458    0x00000000 // TDFI_RDLVL_RESP:RW:0:32:=0x00000000
#define LP3_DENALI_CTL_DATA_459    0x00000000 // RDLVL_GATE_EN:RW:16:1:=0x00 RDLVL_EN:RW:8:1:=0x00 RDLVL_RESP_MASK:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_460    0x00000000 // TDFI_RDLVL_MAX:RW:0:32:=0x00000000
#define LP3_DENALI_CTL_DATA_461    0x00030000 // TDFI_CALVL_EN:RW:16:8:=0x03 RDLVL_GATE_ERROR_STATUS:RD:8:2:=0x00 RDLVL_ERROR_STATUS:RD:0:2:=0x00
#define LP3_DENALI_CTL_DATA_462    0x0008001A // TDFI_CALVL_CAPTURE:RW:16:10:=0x0008 TDFI_CALVL_CC:RW:0:10:=0x001a
#define LP3_DENALI_CTL_DATA_463    0x000B001D // TDFI_CALVL_CAPTURE_F1:RW:16:10:=0x000b TDFI_CALVL_CC_F1:RW:0:10:=0x001d
#define LP3_DENALI_CTL_DATA_464    0x000E0020 // TDFI_CALVL_CAPTURE_F2:RW:16:10:=0x000e TDFI_CALVL_CC_F2:RW:0:10:=0x0020
#define LP3_DENALI_CTL_DATA_465    0x000E0020 // TDFI_CALVL_CAPTURE_F3:RW:16:10:=0x000e TDFI_CALVL_CC_F3:RW:0:10:=0x0020
#define LP3_DENALI_CTL_DATA_466    0x0008001A // TDFI_CALVL_CAPTURE_F4:RW:16:10:=0x0008 TDFI_CALVL_CC_F4:RW:0:10:=0x001a
#define LP3_DENALI_CTL_DATA_467    0x00000000 // TDFI_CALVL_RESP:RW:0:32:=0x00000000
#define LP3_DENALI_CTL_DATA_468    0x00000000 // TDFI_CALVL_MAX:RW:0:32:=0x00000000
#define LP3_DENALI_CTL_DATA_469    0x01000000 // TDFI_PHY_WRDATA:RW:24:3:=0x01 CALVL_ERROR_STATUS:RD:16:4:=0x00 CALVL_EN:RW:8:1:=0x00 CALVL_RESP_MASK:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_470    0x02030101 // TDFI_WRCSLAT_F1:RW:24:7:=0x02 TDFI_RDCSLAT_F1:RW:16:7:=0x03 TDFI_WRCSLAT:RW:8:7:=0x01 TDFI_RDCSLAT:RW:0:7:=0x01
#define LP3_DENALI_CTL_DATA_471    0x00070007 // TDFI_WRCSLAT_F3:RW:24:7:=0x00 TDFI_RDCSLAT_F3:RW:16:7:=0x07 TDFI_WRCSLAT_F2:RW:8:7:=0x00 TDFI_RDCSLAT_F2:RW:0:7:=0x07
#define LP3_DENALI_CTL_DATA_472    0x01050101 // EN_1T_TIMING:RW:24:1:=0x01 TDFI_WRDATA_DELAY:RW:16:8:=0x05 TDFI_WRCSLAT_F4:RW:8:7:=0x01 TDFI_RDCSLAT_F4:RW:0:7:=0x01
#define LP3_DENALI_CTL_DATA_473    0x01010001 // RESERVED:RW_D:24:3:=0x01 MULTI_CHANNEL_ZQ_CAL_MASTER:RW_D:16:1:=0x01 BL_ON_FLY_ENABLE:RW_D:8:1:=0x00 DISABLE_MEMORY_MASKED_WRITE:RW_D:0:1:=0x01
#define LP3_DENALI_CTL_DATA_474    0x01010101 // RESERVED:RW_D:24:3:=0x01 RESERVED:RW_D:16:3:=0x01 RESERVED:RW_D:8:3:=0x01 RESERVED:RW_D:0:3:=0x01
#define LP3_DENALI_CTL_DATA_475    0x00010001 // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x01 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:3:=0x01
#define LP3_DENALI_CTL_DATA_476    0x01010001 // RESERVED:RW_D:24:4:=0x01 RESERVED:RW_D:16:4:=0x01 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x01
#define LP3_DENALI_CTL_DATA_477    0x02000100 // RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x01 RESERVED:RW_D:0:4:=0x00
#define LP3_DENALI_CTL_DATA_478    0x00000100 // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x01 RESERVED:RW_D:0:4:=0x00
#define LP3_DENALI_CTL_DATA_479    0x02000201 // RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x01
#define LP3_DENALI_CTL_DATA_480    0x00000000 // RESERVED:RW_D:0:4:=0x00

#else
#ifdef LP3_F0_153
    //{{{
    #define LP3_DENALI_CTL_DATA_0    	0x00000700 // VERSION:RD:16:16:=0x0000 DRAM_CLASS:RW:8:4:=0x07 START:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_1    	0x00000000 // READ_DATA_FIFO_DEPTH:RD:24:8:=0x00 MAX_CS_REG:RD:16:2:=0x00 MAX_COL_REG:RD:8:4:=0x00 MAX_ROW_REG:RD:0:5:=0x00
    #define LP3_DENALI_CTL_DATA_2    	0x00000000 // MEMCD_RMODW_FIFO_DEPTH:RD:24:8:=0x00 WRITE_DATA_FIFO_PTR_WIDTH:RD:16:8:=0x00 WRITE_DATA_FIFO_DEPTH:RD:8:8:=0x00 READ_DATA_FIFO_PTR_WIDTH:RD:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_3    	0x00000000 // AXI0_RDFIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI0_CMDFIFO_LOG2_DEPTH:RD:16:8:=0x00 ASYNC_CDC_STAGES:RD:8:8:=0x00 MEMCD_RMODW_FIFO_PTR_WIDTH:RD:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_4    	0x00000000 // AXI1_CMDFIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI0_TRANS_WRFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI0_WR_ARRAY_LOG2_DEPTH:RD:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_5    	0x00000000 // AXI1_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI1_TRANS_WRFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI1_WR_ARRAY_LOG2_DEPTH:RD:8:8:=0x00 AXI1_RDFIFO_LOG2_DEPTH:RD:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_6    	0x00000000 // AXI2_TRANS_WRFIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI2_WR_ARRAY_LOG2_DEPTH:RD:16:8:=0x00 AXI2_RDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI2_CMDFIFO_LOG2_DEPTH:RD:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_7    	0x00000000 // AXI3_WR_ARRAY_LOG2_DEPTH:RD:24:8:=0x00 AXI3_RDFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI3_CMDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI2_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_8    	0x00000000 // AXI4_RDFIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI4_CMDFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI3_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI3_TRANS_WRFIFO_LOG2_DEPTH:RD:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_9    	0x00000000 // AXI5_CMDFIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI4_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI4_TRANS_WRFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI4_WR_ARRAY_LOG2_DEPTH:RD:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_10    	0x00000000 // AXI5_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI5_TRANS_WRFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI5_WR_ARRAY_LOG2_DEPTH:RD:8:8:=0x00 AXI5_RDFIFO_LOG2_DEPTH:RD:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_11    	0x00001000 // TINIT_F0:RW:8:24:=0x000010 DFS_CLOSE_BANKS:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_12    	0x0000001F // TINIT3_F0:RW:0:24:=0x00001f
    #define LP3_DENALI_CTL_DATA_13    	0x00000001 // TINIT4_F0:RW:0:24:=0x000001
    #define LP3_DENALI_CTL_DATA_14    	0x00000010 // TINIT5_F0:RW:0:24:=0x000010
    #define LP3_DENALI_CTL_DATA_15    	0x0000002E // TINIT_F1:RW:0:24:=0x00002e
    #define LP3_DENALI_CTL_DATA_16    	0x0000005C // TINIT3_F1:RW:0:24:=0x00005c
    #define LP3_DENALI_CTL_DATA_17    	0x00000001 // TINIT4_F1:RW:0:24:=0x000001
    #define LP3_DENALI_CTL_DATA_18    	0x0000002E // TINIT5_F1:RW:0:24:=0x00002e
    #define LP3_DENALI_CTL_DATA_19    	0x0000003E // TINIT_F2:RW:0:24:=0x00003e
    #define LP3_DENALI_CTL_DATA_20    	0x0000007B // TINIT3_F2:RW:0:24:=0x00007b
    #define LP3_DENALI_CTL_DATA_21    	0x00000001 // TINIT4_F2:RW:0:24:=0x000001
    #define LP3_DENALI_CTL_DATA_22    	0x0000003E // TINIT5_F2:RW:0:24:=0x00003e
    #define LP3_DENALI_CTL_DATA_23    	0x0000005C // TINIT_F3:RW:0:24:=0x00005c
    #define LP3_DENALI_CTL_DATA_24    	0x000000B8 // TINIT3_F3:RW:0:24:=0x0000b8
    #define LP3_DENALI_CTL_DATA_25    	0x00000001 // TINIT4_F3:RW:0:24:=0x000001
    #define LP3_DENALI_CTL_DATA_26    	0x0000005C // TINIT5_F3:RW:0:24:=0x00005c
    #define LP3_DENALI_CTL_DATA_27    	0x00000010 // TINIT_F4:RW:0:24:=0x000010
    #define LP3_DENALI_CTL_DATA_28    	0x0000001F // TINIT3_F4:RW:0:24:=0x00001f
    #define LP3_DENALI_CTL_DATA_29    	0x00000001 // TINIT4_F4:RW:0:24:=0x000001
    #define LP3_DENALI_CTL_DATA_30    	0x00000010 // NO_AUTO_MRR_INIT:RW:24:1:=0x00 TINIT5_F4:RW:0:24:=0x000010
    #define LP3_DENALI_CTL_DATA_31    	0x00000000 // NO_MRW_INIT:RW:24:1:=0x00 NO_MRW_BT_INIT:RW:16:1:=0x00 DFI_INV_DATA_CS:RW:8:1:=0x00 MRR_ERROR_STATUS:RD:0:2:=0x00
    #define LP3_DENALI_CTL_DATA_32    	0x00000101 // DFIBUS_BOOT_FREQ:RW:24:3:=0x00 DFIBUS_FREQ_INIT:RW:16:3:=0x00 PHY_INDEP_TRAIN_MODE:RW:8:1:=0x01 NO_PHY_IND_TRAIN_INIT:RW:0:1:=0x01
    #define LP3_DENALI_CTL_DATA_33    	0x03020100 // DFIBUS_FREQ_F3:RW:24:5:=0x03 DFIBUS_FREQ_F2:RW:16:5:=0x02 DFIBUS_FREQ_F1:RW:8:5:=0x01 DFIBUS_FREQ_F0:RW:0:5:=0x00
    #define LP3_DENALI_CTL_DATA_34    	0x00000004 // DFIBUS_FREQ_F4:RW:0:5:=0x04
    #define LP3_DENALI_CTL_DATA_35    	0x0000001F // TRST_PWRON:RW:0:32:=0x0000001f
    #define LP3_DENALI_CTL_DATA_36    	0x0000004D // CKE_INACTIVE:RW:0:32:=0x0000004d
    #define LP3_DENALI_CTL_DATA_37    	0x0410030C // WRLAT_F1:RW:24:7:=0x04 CASLAT_LIN_F1:RW:16:7:=0x10 WRLAT_F0:RW:8:7:=0x03 CASLAT_LIN_F0:RW:0:7:=0x0c
    #define LP3_DENALI_CTL_DATA_38    	0x081C0614 // WRLAT_F3:RW:24:7:=0x08 CASLAT_LIN_F3:RW:16:7:=0x1c WRLAT_F2:RW:8:7:=0x06 CASLAT_LIN_F2:RW:0:7:=0x14
    #define LP3_DENALI_CTL_DATA_39    	0x0404030C // TCCD:RW:24:5:=0x04 TBST_INT_INTERVAL:RW:16:3:=0x04 WRLAT_F4:RW:8:7:=0x03 CASLAT_LIN_F4:RW:0:7:=0x0c
    #define LP3_DENALI_CTL_DATA_40    	0x070A0200 // TRAS_MIN_F0:RW:24:8:=0x07 TRC_F0:RW:16:8:=0x0a TRRD_F0:RW:8:8:=0x02 TCCDMW:RW:0:6:=0x00
    #define LP3_DENALI_CTL_DATA_41    	0x01080304 // CA_DEFAULT_VAL_F0:RW:24:1:=0x01 TFAW_F0:RW:16:8:=0x08 TRP_F0:RW:8:8:=0x03 TWTR_F0:RW:0:6:=0x04
    #define LP3_DENALI_CTL_DATA_42    	0x04141D05 // TWTR_F1:RW:24:6:=0x04 TRAS_MIN_F1:RW:16:8:=0x14 TRC_F1:RW:8:8:=0x1d TRRD_F1:RW:0:8:=0x05
    #define LP3_DENALI_CTL_DATA_43    	0x07011709 // TRRD_F2:RW:24:8:=0x07 CA_DEFAULT_VAL_F1:RW:16:1:=0x01 TFAW_F1:RW:8:8:=0x17 TRP_F1:RW:0:8:=0x09
    #define LP3_DENALI_CTL_DATA_44    	0x0C051A27 // TRP_F2:RW:24:8:=0x0c TWTR_F2:RW:16:6:=0x05 TRAS_MIN_F2:RW:8:8:=0x1a TRC_F2:RW:0:8:=0x27
    #define LP3_DENALI_CTL_DATA_45    	0x3A0A011F // TRC_F3:RW:24:8:=0x3a TRRD_F3:RW:16:8:=0x0a CA_DEFAULT_VAL_F2:RW:8:1:=0x01 TFAW_F2:RW:0:8:=0x1f
    #define LP3_DENALI_CTL_DATA_46    	0x2E110727 // TFAW_F3:RW:24:8:=0x2e TRP_F3:RW:16:8:=0x11 TWTR_F3:RW:8:6:=0x07 TRAS_MIN_F3:RW:0:8:=0x27
    #define LP3_DENALI_CTL_DATA_47    	0x070A0201 // TRAS_MIN_F4:RW:24:8:=0x07 TRC_F4:RW:16:8:=0x0a TRRD_F4:RW:8:8:=0x02 CA_DEFAULT_VAL_F3:RW:0:1:=0x01
    #define LP3_DENALI_CTL_DATA_48    	0x01080304 // CA_DEFAULT_VAL_F4:RW:24:1:=0x01 TFAW_F4:RW:16:8:=0x08 TRP_F4:RW:8:8:=0x03 TWTR_F4:RW:0:6:=0x04
    #define LP3_DENALI_CTL_DATA_49    	0x000A0A04 // TMOD_F0:RW:16:8:=0x0a TMRD_F0:RW:8:8:=0x0a TRTP_F0:RW:0:8:=0x04
    #define LP3_DENALI_CTL_DATA_50    	0x030029D5 // TCKE_F0:RW:24:4:=0x03 TRAS_MAX_F0:RW:0:17:=0x0029d5
    #define LP3_DENALI_CTL_DATA_51    	0x0A0A0403 // TMOD_F1:RW:24:8:=0x0a TMRD_F1:RW:16:8:=0x0a TRTP_F1:RW:8:8:=0x04 TCKESR_F0:RW:0:8:=0x03
    #define LP3_DENALI_CTL_DATA_52    	0x04007DC6 // TCKE_F1:RW:24:4:=0x04 TRAS_MAX_F1:RW:0:17:=0x007dc6
    #define LP3_DENALI_CTL_DATA_53    	0x0A0A0507 // TMOD_F2:RW:24:8:=0x0a TMRD_F2:RW:16:8:=0x0a TRTP_F2:RW:8:8:=0x05 TCKESR_F1:RW:0:8:=0x07
    #define LP3_DENALI_CTL_DATA_54    	0x0500A7A6 // TCKE_F2:RW:24:4:=0x05 TRAS_MAX_F2:RW:0:17:=0x00a7a6
    #define LP3_DENALI_CTL_DATA_55    	0x0A0A070A // TMOD_F3:RW:24:8:=0x0a TMRD_F3:RW:16:8:=0x0a TRTP_F3:RW:8:8:=0x07 TCKESR_F2:RW:0:8:=0x0a
    #define LP3_DENALI_CTL_DATA_56    	0x0700FB8D // TCKE_F3:RW:24:4:=0x07 TRAS_MAX_F3:RW:0:17:=0x00fb8d
    #define LP3_DENALI_CTL_DATA_57    	0x0A0A040E // TMOD_F4:RW:24:8:=0x0a TMRD_F4:RW:16:8:=0x0a TRTP_F4:RW:8:8:=0x04 TCKESR_F3:RW:0:8:=0x0e
    #define LP3_DENALI_CTL_DATA_58    	0x030029D5 // TCKE_F4:RW:24:4:=0x03 TRAS_MAX_F4:RW:0:17:=0x0029d5
    #define LP3_DENALI_CTL_DATA_59    	0x02030003 // RESERVED:RW:24:3:=0x02 RESERVED:RW:16:3:=0x03 TPPD:RW_D:8:3:=0x00 TCKESR_F4:RW:0:8:=0x03
    #define LP3_DENALI_CTL_DATA_60    	0x09040300 // TRCD_F1:RW:24:8:=0x09 TWR_F0:RW:16:6:=0x04 TRCD_F0:RW:8:8:=0x03 WRITEINTERP:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_61    	0x110A0C07 // TRCD_F3:RW:24:8:=0x11 TWR_F2:RW:16:6:=0x0a TRCD_F2:RW:8:8:=0x0c TWR_F1:RW:0:6:=0x07
    #define LP3_DENALI_CTL_DATA_62    	0x0404030E // TMRR:RW:24:4:=0x04 TWR_F4:RW:16:6:=0x04 TRCD_F4:RW:8:8:=0x03 TWR_F3:RW:0:6:=0x0e
    #define LP3_DENALI_CTL_DATA_63    	0x14000A0A // TCAMRD:RW:24:6:=0x14 TCAENT:RW:8:10:=0x000a TCACKEL:RW:0:5:=0x0a
    #define LP3_DENALI_CTL_DATA_64    	0x02010A0A // TMRZ_F1:RW:24:5:=0x02 TMRZ_F0:RW:16:5:=0x01 TCACKEH:RW:8:5:=0x0a TCAEXT:RW:0:5:=0x0a
    #define LP3_DENALI_CTL_DATA_65    	0x00010302 // AP:RW:24:1:=0x00 TMRZ_F4:RW:16:5:=0x01 TMRZ_F3:RW:8:5:=0x03 TMRZ_F2:RW:0:5:=0x02
    #define LP3_DENALI_CTL_DATA_66    	0x11090101 // TDAL_F1:RW:24:8:=0x11 TDAL_F0:RW:16:8:=0x09 TRAS_LOCKOUT:RW:8:1:=0x01 CONCURRENTAP:RW:0:1:=0x01
    #define LP3_DENALI_CTL_DATA_67    	0x03091F16 // BSTLEN:RW_D:24:5:=0x03 TDAL_F4:RW:16:8:=0x09 TDAL_F3:RW:8:8:=0x1f TDAL_F2:RW:0:8:=0x16
    #define LP3_DENALI_CTL_DATA_68    	0x140D0A04 // TRP_AB_F3:RW:24:8:=0x14 TRP_AB_F2:RW:16:8:=0x0d TRP_AB_F1:RW:8:8:=0x0a TRP_AB_F0:RW:0:8:=0x04
    #define LP3_DENALI_CTL_DATA_69    	0x01010004 // RESERVED:RW:24:1:=0x01 OPTIMAL_RMODW_EN:RW:16:1:=0x01 REG_DIMM_ENABLE:RW:8:1:=0x00 TRP_AB_F4:RW:0:8:=0x04
    #define LP3_DENALI_CTL_DATA_70    	0x01000000 // TREF_ENABLE:RW:24:1:=0x01 RESERVED:RW:16:1:=0x00 AREFRESH:WR:8:1:=0x00 NO_MEMORY_DM:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_71    	0x00002103 // TRFC_F0:RW:8:10:=0x0021 RESERVED:RW:0:3:=0x03
    #define LP3_DENALI_CTL_DATA_72    	0x0061024C // TRFC_F1:RW:16:10:=0x0061 TREF_F0:RW:0:16:=0x024c
    #define LP3_DENALI_CTL_DATA_73    	0x008106F9 // TRFC_F2:RW:16:10:=0x0081 TREF_F1:RW:0:16:=0x06f9
    #define LP3_DENALI_CTL_DATA_74    	0x00C2094F // TRFC_F3:RW:16:10:=0x00c2 TREF_F2:RW:0:16:=0x094f
    #define LP3_DENALI_CTL_DATA_75    	0x00210DFB // TRFC_F4:RW:16:10:=0x0021 TREF_F3:RW:0:16:=0x0dfb
    #define LP3_DENALI_CTL_DATA_76    	0x0000024C // TREF_F4:RW:0:16:=0x024c
    #define LP3_DENALI_CTL_DATA_77    	0x00040003 // TPDEX_F1:RW:16:16:=0x0004 TPDEX_F0:RW:0:16:=0x0003
    #define LP3_DENALI_CTL_DATA_78    	0x00070005 // TPDEX_F3:RW:16:16:=0x0007 TPDEX_F2:RW:0:16:=0x0005
    #define LP3_DENALI_CTL_DATA_79    	0x00000003 // SHUTDOWN_STATUS:RD:24:6:=0x00 SHUTDOWN_MEM_GATE:RW:16:1:=0x00 TPDEX_F4:RW:0:16:=0x0003
    #define LP3_DENALI_CTL_DATA_80    	0x110C0903 // TMRRI_F3:RW:24:8:=0x11 TMRRI_F2:RW:16:8:=0x0c TMRRI_F1:RW:8:8:=0x09 TMRRI_F0:RW:0:8:=0x03
    #define LP3_DENALI_CTL_DATA_81    	0x00000003 // TCKEHCS_F0:RW:24:4:=0x00 TCKELCS_F0:RW:16:4:=0x00 TCSCKE_F0:RW:8:4:=0x00 TMRRI_F4:RW:0:8:=0x03
    #define LP3_DENALI_CTL_DATA_82    	0x00000000 // TCKELCS_F1:RW:24:4:=0x00 TCSCKE_F1:RW:16:4:=0x00 TZQCKE_F0:RW:8:4:=0x00 TMRWCKEL_F0:RW:0:5:=0x00
    #define LP3_DENALI_CTL_DATA_83    	0x00000000 // TCSCKE_F2:RW:24:4:=0x00 TZQCKE_F1:RW:16:4:=0x00 TMRWCKEL_F1:RW:8:5:=0x00 TCKEHCS_F1:RW:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_84    	0x00000000 // TZQCKE_F2:RW:24:4:=0x00 TMRWCKEL_F2:RW:16:5:=0x00 TCKEHCS_F2:RW:8:4:=0x00 TCKELCS_F2:RW:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_85    	0x00000000 // TMRWCKEL_F3:RW:24:5:=0x00 TCKEHCS_F3:RW:16:4:=0x00 TCKELCS_F3:RW:8:4:=0x00 TCSCKE_F3:RW:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_86    	0x00000000 // TCKEHCS_F4:RW:24:4:=0x00 TCKELCS_F4:RW:16:4:=0x00 TCSCKE_F4:RW:8:4:=0x00 TZQCKE_F3:RW:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_87    	0x00220000 // TXSR_F0:RW:16:16:=0x0022 TZQCKE_F4:RW:8:4:=0x00 TMRWCKEL_F4:RW:0:5:=0x00
    #define LP3_DENALI_CTL_DATA_88    	0x00660022 // TXSR_F1:RW:16:16:=0x0066 TXSNR_F0:RW:0:16:=0x0022
    #define LP3_DENALI_CTL_DATA_89    	0x00870066 // TXSR_F2:RW:16:16:=0x0087 TXSNR_F1:RW:0:16:=0x0066
    #define LP3_DENALI_CTL_DATA_90    	0x00CB0087 // TXSR_F3:RW:16:16:=0x00cb TXSNR_F2:RW:0:16:=0x0087
    #define LP3_DENALI_CTL_DATA_91    	0x002200CB // TXSR_F4:RW:16:16:=0x0022 TXSNR_F3:RW:0:16:=0x00cb
    #define LP3_DENALI_CTL_DATA_92    	0x00000022 // TCKEHCMD_F0:RW:24:4:=0x00 TCKELCMD_F0:RW:16:4:=0x00 TXSNR_F4:RW:0:16:=0x0022
    #define LP3_DENALI_CTL_DATA_93    	0x00000000 // TCKELPD_F0:RW:24:4:=0x00 TESCKE_F0:RW:16:3:=0x00 TSR_F0:RW:8:8:=0x00 TCKCKEL_F0:RW:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_94    	0x00000000 // TCKEHCMD_F1:RW:24:4:=0x00 TCKELCMD_F1:RW:16:4:=0x00 TCMDCKE_F0:RW:8:4:=0x00 TCSCKEH_F0:RW:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_95    	0x00000000 // TCKELPD_F1:RW:24:4:=0x00 TESCKE_F1:RW:16:3:=0x00 TSR_F1:RW:8:8:=0x00 TCKCKEL_F1:RW:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_96    	0x00000000 // TCKEHCMD_F2:RW:24:4:=0x00 TCKELCMD_F2:RW:16:4:=0x00 TCMDCKE_F1:RW:8:4:=0x00 TCSCKEH_F1:RW:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_97    	0x00000000 // TCKELPD_F2:RW:24:4:=0x00 TESCKE_F2:RW:16:3:=0x00 TSR_F2:RW:8:8:=0x00 TCKCKEL_F2:RW:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_98    	0x00000000 // TCKEHCMD_F3:RW:24:4:=0x00 TCKELCMD_F3:RW:16:4:=0x00 TCMDCKE_F2:RW:8:4:=0x00 TCSCKEH_F2:RW:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_99    	0x00000000 // TCKELPD_F3:RW:24:4:=0x00 TESCKE_F3:RW:16:3:=0x00 TSR_F3:RW:8:8:=0x00 TCKCKEL_F3:RW:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_100    	0x00000000 // TCKEHCMD_F4:RW:24:4:=0x00 TCKELCMD_F4:RW:16:4:=0x00 TCMDCKE_F3:RW:8:4:=0x00 TCSCKEH_F3:RW:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_101    	0x00000000 // TCKELPD_F4:RW:24:4:=0x00 TESCKE_F4:RW:16:3:=0x00 TSR_F4:RW:8:8:=0x00 TCKCKEL_F4:RW:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_102    	0x00000000 // SREFRESH_EXIT_NO_REFRESH:RW:24:1:=0x00 PWRUP_SREFRESH_EXIT:RW:16:1:=0x00 TCMDCKE_F4:RW:8:4:=0x00 TCSCKEH_F4:RW:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_103    	0x00000301 // RESERVED:WR:16:9:=0x0000 CKE_DELAY:RW:8:3:=0x03 ENABLE_QUICK_SREFRESH:RW:0:1:=0x01
    #define LP3_DENALI_CTL_DATA_104    	0x00000100 // DFS_WRLVL_EN:RW:24:1:=0x00 DFS_CALVL_EN:RW:16:1:=0x00 DFS_ZQ_EN:RW:8:1:=0x01 DFS_STATUS:RD:0:2:=0x00
    #define LP3_DENALI_CTL_DATA_105    	0x00000000 // DFS_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 DFS_RDLVL_GATE_EN:RW:8:1:=0x00 DFS_RDLVL_EN:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_106    	0x00000000 // DFS_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 DFS_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_107    	0x00000000 // DFS_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 DFS_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_108    	0x01000000 // RESERVED:RW:24:3:=0x01 ZQ_CALINIT_CS_CL_STATUS:RD:16:2:=0x00 ZQ_CALLATCH_STATUS:RD:8:2:=0x00 ZQ_CALSTART_STATUS:RD:0:2:=0x00
    #define LP3_DENALI_CTL_DATA_109    	0x80104002 // RESERVED:RW:24:8:=0x80 RESERVED:RW:16:8:=0x10 RESERVED:RW:8:8:=0x40 RESERVED:RW:0:3:=0x02
    #define LP3_DENALI_CTL_DATA_110    	0x00040003 // UPD_CTRLUPD_HIGH_THRESHOLD_F0:RW:16:16:=0x0004 UPD_CTRLUPD_NORM_THRESHOLD_F0:RW:0:16:=0x0003
    #define LP3_DENALI_CTL_DATA_111    	0x00040005 // UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0004 UPD_CTRLUPD_TIMEOUT_F0:RW:0:16:=0x0005
    #define LP3_DENALI_CTL_DATA_112    	0x00030000 // UPD_CTRLUPD_NORM_THRESHOLD_F1:RW:16:16:=0x0003 UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_113    	0x00050004 // UPD_CTRLUPD_TIMEOUT_F1:RW:16:16:=0x0005 UPD_CTRLUPD_HIGH_THRESHOLD_F1:RW:0:16:=0x0004
    #define LP3_DENALI_CTL_DATA_114    	0x00000004 // UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0004
    #define LP3_DENALI_CTL_DATA_115    	0x00040003 // UPD_CTRLUPD_HIGH_THRESHOLD_F2:RW:16:16:=0x0004 UPD_CTRLUPD_NORM_THRESHOLD_F2:RW:0:16:=0x0003
    #define LP3_DENALI_CTL_DATA_116    	0x00040005 // UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0004 UPD_CTRLUPD_TIMEOUT_F2:RW:0:16:=0x0005
    #define LP3_DENALI_CTL_DATA_117    	0x00030000 // UPD_CTRLUPD_NORM_THRESHOLD_F3:RW:16:16:=0x0003 UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_118    	0x00050004 // UPD_CTRLUPD_TIMEOUT_F3:RW:16:16:=0x0005 UPD_CTRLUPD_HIGH_THRESHOLD_F3:RW:0:16:=0x0004
    #define LP3_DENALI_CTL_DATA_119    	0x00000004 // UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0004
    #define LP3_DENALI_CTL_DATA_120    	0x00040003 // UPD_CTRLUPD_HIGH_THRESHOLD_F4:RW:16:16:=0x0004 UPD_CTRLUPD_NORM_THRESHOLD_F4:RW:0:16:=0x0003
    #define LP3_DENALI_CTL_DATA_121    	0x00040005 // UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0004 UPD_CTRLUPD_TIMEOUT_F4:RW:0:16:=0x0005
    #define LP3_DENALI_CTL_DATA_122    	0x09300000 // TDFI_PHYMSTR_MAX_F0:RW:16:16:=0x0930 UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_123    	0x00000498 // PHYMSTR_DFI_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 TDFI_PHYMSTR_RESP_F0:RW:0:16:=0x0498
    #define LP3_DENALI_CTL_DATA_124    	0x0DF21BE4 // TDFI_PHYMSTR_RESP_F1:RW:16:16:=0x0df2 TDFI_PHYMSTR_MAX_F1:RW:0:16:=0x1be4
    #define LP3_DENALI_CTL_DATA_125    	0x253C0000 // TDFI_PHYMSTR_MAX_F2:RW:16:16:=0x253c PHYMSTR_DFI_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_126    	0x0000129E // PHYMSTR_DFI_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 TDFI_PHYMSTR_RESP_F2:RW:0:16:=0x129e
    #define LP3_DENALI_CTL_DATA_127    	0x1BF637EC // TDFI_PHYMSTR_RESP_F3:RW:16:16:=0x1bf6 TDFI_PHYMSTR_MAX_F3:RW:0:16:=0x37ec
    #define LP3_DENALI_CTL_DATA_128    	0x09300000 // TDFI_PHYMSTR_MAX_F4:RW:16:16:=0x0930 PHYMSTR_DFI_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_129    	0x00000498 // PHYMSTR_DFI_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 TDFI_PHYMSTR_RESP_F4:RW:0:16:=0x0498
    #define LP3_DENALI_CTL_DATA_130    	0x00000000 // MRR_TEMPCHK_NORM_THRESHOLD_F0:RW:16:16:=0x0000 PHYMSTR_ERROR_STATUS:RD:8:2:=0x00 PHYMSTR_NO_AREF:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_131    	0x00000000 // MRR_TEMPCHK_TIMEOUT_F0:RW:16:16:=0x0000 MRR_TEMPCHK_HIGH_THRESHOLD_F0:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_132    	0x00000000 // MRR_TEMPCHK_HIGH_THRESHOLD_F1:RW:16:16:=0x0000 MRR_TEMPCHK_NORM_THRESHOLD_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_133    	0x00000000 // MRR_TEMPCHK_NORM_THRESHOLD_F2:RW:16:16:=0x0000 MRR_TEMPCHK_TIMEOUT_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_134    	0x00000000 // MRR_TEMPCHK_TIMEOUT_F2:RW:16:16:=0x0000 MRR_TEMPCHK_HIGH_THRESHOLD_F2:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_135    	0x00000000 // MRR_TEMPCHK_HIGH_THRESHOLD_F3:RW:16:16:=0x0000 MRR_TEMPCHK_NORM_THRESHOLD_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_136    	0x00000000 // MRR_TEMPCHK_NORM_THRESHOLD_F4:RW:16:16:=0x0000 MRR_TEMPCHK_TIMEOUT_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_137    	0x00000000 // MRR_TEMPCHK_TIMEOUT_F4:RW:16:16:=0x0000 MRR_TEMPCHK_HIGH_THRESHOLD_F4:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_138    	0x02020200 // CKSRE_F1:RW:24:8:=0x02 CKSRX_F0:RW:16:8:=0x02 CKSRE_F0:RW:8:8:=0x02 LOWPOWER_REFRESH_ENABLE:RW:0:2:=0x00
    #define LP3_DENALI_CTL_DATA_139    	0x02020202 // CKSRE_F3:RW:24:8:=0x02 CKSRX_F2:RW:16:8:=0x02 CKSRE_F2:RW:8:8:=0x02 CKSRX_F1:RW:0:8:=0x02
    #define LP3_DENALI_CTL_DATA_140    	0x00020202 // CKSRX_F4:RW:16:8:=0x02 CKSRE_F4:RW:8:8:=0x02 CKSRX_F3:RW:0:8:=0x02
    #define LP3_DENALI_CTL_DATA_141    	0x02000000 // LPI_SR_WAKEUP_F0:RW:24:4:=0x02 LPI_PD_WAKEUP_F0:RW:16:4:=0x00 LP_CMD:WR:0:9:=0x0000
    #define LP3_DENALI_CTL_DATA_142    	0x07030203 // LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F0:RW:24:4:=0x07 LPI_SRPD_DEEP_WAKEUP_F0:RW:16:4:=0x03 LPI_SRPD_LITE_WAKEUP_F0:RW:8:4:=0x02 LPI_SR_MCCLK_GATE_WAKEUP_F0:RW:0:4:=0x03
    #define LP3_DENALI_CTL_DATA_143    	0x0200040F // LPI_SR_WAKEUP_F1:RW:24:4:=0x02 LPI_PD_WAKEUP_F1:RW:16:4:=0x00 LPI_TIMER_WAKEUP_F0:RW:8:4:=0x04 LPI_DPD_WAKEUP_F0:RW:0:4:=0x0f
    #define LP3_DENALI_CTL_DATA_144    	0x07030203 // LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F1:RW:24:4:=0x07 LPI_SRPD_DEEP_WAKEUP_F1:RW:16:4:=0x03 LPI_SRPD_LITE_WAKEUP_F1:RW:8:4:=0x02 LPI_SR_MCCLK_GATE_WAKEUP_F1:RW:0:4:=0x03
    #define LP3_DENALI_CTL_DATA_145    	0x0200040F // LPI_SR_WAKEUP_F2:RW:24:4:=0x02 LPI_PD_WAKEUP_F2:RW:16:4:=0x00 LPI_TIMER_WAKEUP_F1:RW:8:4:=0x04 LPI_DPD_WAKEUP_F1:RW:0:4:=0x0f
    #define LP3_DENALI_CTL_DATA_146    	0x07030203 // LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F2:RW:24:4:=0x07 LPI_SRPD_DEEP_WAKEUP_F2:RW:16:4:=0x03 LPI_SRPD_LITE_WAKEUP_F2:RW:8:4:=0x02 LPI_SR_MCCLK_GATE_WAKEUP_F2:RW:0:4:=0x03
    #define LP3_DENALI_CTL_DATA_147    	0x0200040F // LPI_SR_WAKEUP_F3:RW:24:4:=0x02 LPI_PD_WAKEUP_F3:RW:16:4:=0x00 LPI_TIMER_WAKEUP_F2:RW:8:4:=0x04 LPI_DPD_WAKEUP_F2:RW:0:4:=0x0f
    #define LP3_DENALI_CTL_DATA_148    	0x07030203 // LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F3:RW:24:4:=0x07 LPI_SRPD_DEEP_WAKEUP_F3:RW:16:4:=0x03 LPI_SRPD_LITE_WAKEUP_F3:RW:8:4:=0x02 LPI_SR_MCCLK_GATE_WAKEUP_F3:RW:0:4:=0x03
    #define LP3_DENALI_CTL_DATA_149    	0x0200040F // LPI_SR_WAKEUP_F4:RW:24:4:=0x02 LPI_PD_WAKEUP_F4:RW:16:4:=0x00 LPI_TIMER_WAKEUP_F3:RW:8:4:=0x04 LPI_DPD_WAKEUP_F3:RW:0:4:=0x0f
    #define LP3_DENALI_CTL_DATA_150    	0x07030203 // LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F4:RW:24:4:=0x07 LPI_SRPD_DEEP_WAKEUP_F4:RW:16:4:=0x03 LPI_SRPD_LITE_WAKEUP_F4:RW:8:4:=0x02 LPI_SR_MCCLK_GATE_WAKEUP_F4:RW:0:4:=0x03
    #define LP3_DENALI_CTL_DATA_151    	0x000F040F // LPI_WAKEUP_EN:RW:16:5:=0x0f LPI_TIMER_WAKEUP_F4:RW:8:4:=0x04 LPI_DPD_WAKEUP_F4:RW:0:4:=0x0f
    #define LP3_DENALI_CTL_DATA_152    	0x00040003 // LPI_WAKEUP_TIMEOUT:RW:16:12:=0x0004 LPI_TIMER_COUNT:RW:0:12:=0x0003
    #define LP3_DENALI_CTL_DATA_153    	0x00000007 // LP_AUTO_ENTRY_EN:RW:24:4:=0x00 LP_STATE_CS1:RD:16:6:=0x00 LP_STATE_CS0:RD:8:6:=0x00 TDFI_LP_RESP:RW:0:3:=0x07
    #define LP3_DENALI_CTL_DATA_154    	0x00000000 // LP_AUTO_PD_IDLE:RW:16:12:=0x0000 LP_AUTO_MEM_GATE_EN:RW:8:3:=0x00 LP_AUTO_EXIT_EN:RW:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_155    	0x00000000 // LP_AUTO_SR_MC_GATE_IDLE:RW:24:8:=0x00 LP_AUTO_SR_IDLE:RW:16:8:=0x00 LP_AUTO_SRPD_LITE_IDLE:RW:0:12:=0x0000
    #define LP3_DENALI_CTL_DATA_156    	0x00000000 // HW_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 HW_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_157    	0x00000000 // HW_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 HW_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_158    	0x00000000 // LPC_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 HW_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_159    	0x00000000 // LPC_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 LPC_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_160    	0x00000000 // LPC_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 LPC_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_161    	0x00000000 // RESERVED:RW:24:1:=0x00 LPC_SR_PHYMSTR_EN:RW:16:1:=0x00 LPC_SR_PHYUPD_EN:RW:8:1:=0x00 LPC_SR_CTRLUPD_EN:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_162    	0x04040100 // PCPCS_PD_EXIT_DEPTH:RW:24:5:=0x04 PCPCS_PD_ENTER_DEPTH:RW:16:5:=0x04 PCPCS_PD_EN:RW:8:1:=0x01 LPC_SR_ZQ_EN:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_163    	0x00030000 // LP_CS:RW:24:2:=0x00 PCPCS_CS_MAP:RW:16:2:=0x03 PCPCS_PD_MASK:RW:8:2:=0x00 PCPCS_PD_ENTER_TIMER:RW:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_164    	0x00000000 // CS1_IDLE:RD:8:1:=0x00 CS0_IDLE:RD:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_165    	0x0000004D // TDPD_F0:RW:0:24:=0x00004d
    #define LP3_DENALI_CTL_DATA_166    	0x000000E6 // TDPD_F1:RW:0:24:=0x0000e6
    #define LP3_DENALI_CTL_DATA_167    	0x00000133 // TDPD_F2:RW:0:24:=0x000133
    #define LP3_DENALI_CTL_DATA_168    	0x000001CC // TDPD_F3:RW:0:24:=0x0001cc
    #define LP3_DENALI_CTL_DATA_169    	0x0000004D // TDPD_CNT_DONE_STATUS:RD:24:2:=0x00 TDPD_F4:RW:0:24:=0x00004d
    #define LP3_DENALI_CTL_DATA_170    	0xC0010003 // TDFI_INIT_START_F0:RW_D:24:8:=0xc0 DFS_ENABLE:RW:16:1:=0x01 RESERVED:RW:8:8:=0x00 PWRUP_SREFRESH_EXIT_CS:RW:0:2:=0x03
    #define LP3_DENALI_CTL_DATA_171    	0x00C01000 // TDFI_INIT_START_F1:RW_D:16:8:=0xc0 TDFI_INIT_COMPLETE_F0:RW_D:0:16:=0x1000
    #define LP3_DENALI_CTL_DATA_172    	0x00C01000 // TDFI_INIT_START_F2:RW_D:16:8:=0xc0 TDFI_INIT_COMPLETE_F1:RW_D:0:16:=0x1000
    #define LP3_DENALI_CTL_DATA_173    	0x00C01000 // TDFI_INIT_START_F3:RW_D:16:8:=0xc0 TDFI_INIT_COMPLETE_F2:RW_D:0:16:=0x1000
    #define LP3_DENALI_CTL_DATA_174    	0x00C01000 // TDFI_INIT_START_F4:RW_D:16:8:=0xc0 TDFI_INIT_COMPLETE_F3:RW_D:0:16:=0x1000
    #define LP3_DENALI_CTL_DATA_175    	0x01001000 // DFS_PHY_REG_WRITE_EN:RW:24:1:=0x01 CURRENT_REG_COPY:RD:16:3:=0x00 TDFI_INIT_COMPLETE_F4:RW_D:0:16:=0x1000
    #define LP3_DENALI_CTL_DATA_176    	0x00000C00 // DFS_PHY_REG_WRITE_ADDR:RW:0:32:=0x00000c00
    #define LP3_DENALI_CTL_DATA_177    	0x00000000 // DFS_PHY_REG_WRITE_DATA_F0:RW:0:32:=0x00000000
    #define LP3_DENALI_CTL_DATA_178    	0x00000001 // DFS_PHY_REG_WRITE_DATA_F1:RW:0:32:=0x00000001
    #define LP3_DENALI_CTL_DATA_179    	0x00000002 // DFS_PHY_REG_WRITE_DATA_F2:RW:0:32:=0x00000002
    #define LP3_DENALI_CTL_DATA_180    	0x00000003 // DFS_PHY_REG_WRITE_DATA_F3:RW:0:32:=0x00000003
    #define LP3_DENALI_CTL_DATA_181    	0x00000004 // DFS_PHY_REG_WRITE_DATA_F4:RW:0:32:=0x00000004
    #define LP3_DENALI_CTL_DATA_182    	0x0000000E // DFS_PHY_REG_WRITE_MASK:RW:0:4:=0x0e
    #define LP3_DENALI_CTL_DATA_183    	0x00000000 // WRITE_MODEREG:RW+:0:27:=0x00000000
    #define LP3_DENALI_CTL_DATA_184    	0x00000000 // READ_MODEREG:RW+:8:17:=0x000000 MRW_STATUS:RD:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_185    	0x00000000 // PERIPHERAL_MRR_DATA:RD:0:40:=0x00000000
    #define LP3_DENALI_CTL_DATA_186    	0x00000000 // AUTO_TEMPCHK_VAL_0:RD:8:16:=0x0000 PERIPHERAL_MRR_DATA:RD:0:40:=0x00
    #define LP3_DENALI_CTL_DATA_187    	0x00000000 // DISABLE_UPDATE_TVRCG:RW:16:1:=0x00 AUTO_TEMPCHK_VAL_1:RD:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_188    	0x001F0000 // TVRCG_ENABLE_F0:RW:16:10:=0x001f MRW_DFS_UPDATE_FRC:RW:0:3:=0x00
    #define LP3_DENALI_CTL_DATA_189    	0x00270010 // TFC_F0:RW:16:10:=0x0027 TVRCG_DISABLE_F0:RW:0:10:=0x0010
    #define LP3_DENALI_CTL_DATA_190    	0x00270000 // TVREF_LONG_F0:RW:16:16:=0x0027 TCKFSPX_F0:RW:8:5:=0x00 TCKFSPE_F0:RW:0:5:=0x00
    #define LP3_DENALI_CTL_DATA_191    	0x002E005C // TVRCG_DISABLE_F1:RW:16:10:=0x002e TVRCG_ENABLE_F1:RW:0:10:=0x005c
    #define LP3_DENALI_CTL_DATA_192    	0x00000073 // TCKFSPX_F1:RW:24:5:=0x00 TCKFSPE_F1:RW:16:5:=0x00 TFC_F1:RW:0:10:=0x0073
    #define LP3_DENALI_CTL_DATA_193    	0x007B0073 // TVRCG_ENABLE_F2:RW:16:10:=0x007b TVREF_LONG_F1:RW:0:16:=0x0073
    #define LP3_DENALI_CTL_DATA_194    	0x009A003E // TFC_F2:RW:16:10:=0x009a TVRCG_DISABLE_F2:RW:0:10:=0x003e
    #define LP3_DENALI_CTL_DATA_195    	0x009A0000 // TVREF_LONG_F2:RW:16:16:=0x009a TCKFSPX_F2:RW:8:5:=0x00 TCKFSPE_F2:RW:0:5:=0x00
    #define LP3_DENALI_CTL_DATA_196    	0x005C00B8 // TVRCG_DISABLE_F3:RW:16:10:=0x005c TVRCG_ENABLE_F3:RW:0:10:=0x00b8
    #define LP3_DENALI_CTL_DATA_197    	0x000000E6 // TCKFSPX_F3:RW:24:5:=0x00 TCKFSPE_F3:RW:16:5:=0x00 TFC_F3:RW:0:10:=0x00e6
    #define LP3_DENALI_CTL_DATA_198    	0x001F00E6 // TVRCG_ENABLE_F4:RW:16:10:=0x001f TVREF_LONG_F3:RW:0:16:=0x00e6
    #define LP3_DENALI_CTL_DATA_199    	0x00270010 // TFC_F4:RW:16:10:=0x0027 TVRCG_DISABLE_F4:RW:0:10:=0x0010
    #define LP3_DENALI_CTL_DATA_200    	0x00270000 // TVREF_LONG_F4:RW:16:16:=0x0027 TCKFSPX_F4:RW:8:5:=0x00 TCKFSPE_F4:RW:0:5:=0x00
    #define LP3_DENALI_CTL_DATA_201    	0x00000000 // MRR_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 MRR_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_202    	0x00000000 // MRR_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 MRR_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_203    	0x00000000 // MRW_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 MRR_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_204    	0x00000000 // MRW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 MRW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_205    	0x00000000 // MRW_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 MRW_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_206    	0x06C30483 // MR2_DATA_F1_0:RW:24:8:=0x06 MR1_DATA_F1_0:RW:16:8:=0xc3 MR2_DATA_F0_0:RW:8:8:=0x04 MR1_DATA_F0_0:RW:0:8:=0x83
    #define LP3_DENALI_CTL_DATA_207    	0x1C831803 // MR2_DATA_F3_0:RW:24:8:=0x1c MR1_DATA_F3_0:RW:16:8:=0x83 MR2_DATA_F2_0:RW:8:8:=0x18 MR1_DATA_F2_0:RW:0:8:=0x03
    #define LP3_DENALI_CTL_DATA_208    	0x01000483 // MR3_DATA_F0_0:RW:24:8:=0x01 MRSINGLE_DATA_0:RW:16:8:=0x00 MR2_DATA_F4_0:RW:8:8:=0x04 MR1_DATA_F4_0:RW:0:8:=0x83
    #define LP3_DENALI_CTL_DATA_209    	0x01010101 // MR3_DATA_F4_0:RW:24:8:=0x01 MR3_DATA_F3_0:RW:16:8:=0x01 MR3_DATA_F2_0:RW:8:8:=0x01 MR3_DATA_F1_0:RW:0:8:=0x01
    #define LP3_DENALI_CTL_DATA_210    	0x07070700 // MR11_DATA_F2_0:RW:24:8:=0x07 MR11_DATA_F1_0:RW:16:8:=0x07 MR11_DATA_F0_0:RW:8:8:=0x07 MR8_DATA_0:RD:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_211    	0x00000707 // MR12_DATA_F1_0:RW:24:8:=0x00 MR12_DATA_F0_0:RW:16:8:=0x00 MR11_DATA_F4_0:RW:8:8:=0x07 MR11_DATA_F3_0:RW:0:8:=0x07
    #define LP3_DENALI_CTL_DATA_212    	0x00000000 // MR13_DATA_0:RW:24:8:=0x00 MR12_DATA_F4_0:RW:16:8:=0x00 MR12_DATA_F3_0:RW:8:8:=0x00 MR12_DATA_F2_0:RW:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_213    	0x00000000 // MR14_DATA_F3_0:RW:24:8:=0x00 MR14_DATA_F2_0:RW:16:8:=0x00 MR14_DATA_F1_0:RW:8:8:=0x00 MR14_DATA_F0_0:RW:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_214    	0x00000000 // MR_FSP_DATA_VALID_F2_0:RW:24:1:=0x00 MR_FSP_DATA_VALID_F1_0:RW:16:1:=0x00 MR_FSP_DATA_VALID_F0_0:RW:8:1:=0x00 MR14_DATA_F4_0:RW:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_215    	0x00000000 // MR17_DATA_0:RW:24:8:=0x00 MR16_DATA_0:RW:16:8:=0x00 MR_FSP_DATA_VALID_F4_0:RW:8:1:=0x00 MR_FSP_DATA_VALID_F3_0:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_216    	0x00000000 // MR22_DATA_F2_0:RW:24:8:=0x00 MR22_DATA_F1_0:RW:16:8:=0x00 MR22_DATA_F0_0:RW:8:8:=0x00 MR20_DATA_0:RD:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_217    	0x04830000 // MR2_DATA_F0_1:RW:24:8:=0x04 MR1_DATA_F0_1:RW:16:8:=0x83 MR22_DATA_F4_0:RW:8:8:=0x00 MR22_DATA_F3_0:RW:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_218    	0x180306C3 // MR2_DATA_F2_1:RW:24:8:=0x18 MR1_DATA_F2_1:RW:16:8:=0x03 MR2_DATA_F1_1:RW:8:8:=0x06 MR1_DATA_F1_1:RW:0:8:=0xc3
    #define LP3_DENALI_CTL_DATA_219    	0x04831C83 // MR2_DATA_F4_1:RW:24:8:=0x04 MR1_DATA_F4_1:RW:16:8:=0x83 MR2_DATA_F3_1:RW:8:8:=0x1c MR1_DATA_F3_1:RW:0:8:=0x83
    #define LP3_DENALI_CTL_DATA_220    	0x01010100 // MR3_DATA_F2_1:RW:24:8:=0x01 MR3_DATA_F1_1:RW:16:8:=0x01 MR3_DATA_F0_1:RW:8:8:=0x01 MRSINGLE_DATA_1:RW:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_221    	0x07000101 // MR11_DATA_F0_1:RW:24:8:=0x07 MR8_DATA_1:RD:16:8:=0x00 MR3_DATA_F4_1:RW:8:8:=0x01 MR3_DATA_F3_1:RW:0:8:=0x01
    #define LP3_DENALI_CTL_DATA_222    	0x07070707 // MR11_DATA_F4_1:RW:24:8:=0x07 MR11_DATA_F3_1:RW:16:8:=0x07 MR11_DATA_F2_1:RW:8:8:=0x07 MR11_DATA_F1_1:RW:0:8:=0x07
    #define LP3_DENALI_CTL_DATA_223    	0x00000000 // MR12_DATA_F3_1:RW:24:8:=0x00 MR12_DATA_F2_1:RW:16:8:=0x00 MR12_DATA_F1_1:RW:8:8:=0x00 MR12_DATA_F0_1:RW:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_224    	0x00000000 // MR14_DATA_F1_1:RW:24:8:=0x00 MR14_DATA_F0_1:RW:16:8:=0x00 MR13_DATA_1:RW:8:8:=0x00 MR12_DATA_F4_1:RW:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_225    	0x00000000 // MR_FSP_DATA_VALID_F0_1:RW:24:1:=0x00 MR14_DATA_F4_1:RW:16:8:=0x00 MR14_DATA_F3_1:RW:8:8:=0x00 MR14_DATA_F2_1:RW:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_226    	0x00000000 // MR_FSP_DATA_VALID_F4_1:RW:24:1:=0x00 MR_FSP_DATA_VALID_F3_1:RW:16:1:=0x00 MR_FSP_DATA_VALID_F2_1:RW:8:1:=0x00 MR_FSP_DATA_VALID_F1_1:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_227    	0x00000000 // MR22_DATA_F0_1:RW:24:8:=0x00 MR20_DATA_1:RD:16:8:=0x00 MR17_DATA_1:RW:8:8:=0x00 MR16_DATA_1:RW:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_228    	0x00000000 // MR22_DATA_F4_1:RW:24:8:=0x00 MR22_DATA_F3_1:RW:16:8:=0x00 MR22_DATA_F2_1:RW:8:8:=0x00 MR22_DATA_F1_1:RW:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_229    	0x01000000 // FSP_PHY_UPDATE_MRW:RW:24:1:=0x01 RESERVED:RD:16:1:=0x00 RESERVED:RD:8:1:=0x00 RL3_SUPPORT_EN:RD:0:2:=0x00
    #define LP3_DENALI_CTL_DATA_230    	0x00000000 // FSP_WR_CURRENT:RW+:24:1:=0x00 FSP_OP_CURRENT:RW+:16:1:=0x00 FSP_STATUS:RW:8:1:=0x00 DFS_ALWAYS_WRITE_FSP:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_231    	0x00000000 // FSP1_FRC:RW+:24:3:=0x00 FSP0_FRC:RW+:16:3:=0x00 FSP1_FRC_VALID:RW+:8:1:=0x00 FSP0_FRC_VALID:RW+:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_232    	0x01000000 // BIST_DATA_CHECK:RW:24:1:=0x01 ADDR_SPACE:RW:16:6:=0x00 BIST_RESULT:RD:8:2:=0x00 BIST_GO:WR:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_233    	0x00000001 // BIST_ADDR_CHECK:RW:0:1:=0x01
    #define LP3_DENALI_CTL_DATA_234    	0x00000000 // BIST_START_ADDRESS:RW:0:34:=0x00000000
    #define LP3_DENALI_CTL_DATA_235    	0x00000000 // BIST_START_ADDRESS:RW:0:34:=0x00
    #define LP3_DENALI_CTL_DATA_236    	0x00000000 // BIST_DATA_MASK:RW:0:64:=0x00000000
    #define LP3_DENALI_CTL_DATA_237    	0x00000000 // BIST_DATA_MASK:RW:0:64:=0x00000000
    #define LP3_DENALI_CTL_DATA_238    	0x18151100 // AREF_MAX_DEFICIT:RW:24:5:=0x18 AREF_HIGH_THRESHOLD:RW:16:5:=0x15 AREF_NORM_THRESHOLD:RW:8:5:=0x11 LONG_COUNT_MASK:RW:0:5:=0x00
    #define LP3_DENALI_CTL_DATA_239    	0x0000000C // ZQ_CALSTART_NORM_THRESHOLD_F0:RW:8:16:=0x0000 AREF_MAX_CREDIT:RW:0:5:=0x0c
    #define LP3_DENALI_CTL_DATA_240    	0x00000000 // ZQ_CALLATCH_HIGH_THRESHOLD_F0:RW:16:16:=0x0000 ZQ_CALSTART_HIGH_THRESHOLD_F0:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_241    	0x00000000 // ZQ_CS_HIGH_THRESHOLD_F0:RW:16:16:=0x0000 ZQ_CS_NORM_THRESHOLD_F0:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_242    	0x00000000 // ZQ_CALLATCH_TIMEOUT_F0:RW:16:16:=0x0000 ZQ_CALSTART_TIMEOUT_F0:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_243    	0x00000000 // ZQ_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 ZQ_CS_TIMEOUT_F0:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_244    	0x00000000 // ZQ_CALSTART_HIGH_THRESHOLD_F1:RW:16:16:=0x0000 ZQ_CALSTART_NORM_THRESHOLD_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_245    	0x00000000 // ZQ_CS_NORM_THRESHOLD_F1:RW:16:16:=0x0000 ZQ_CALLATCH_HIGH_THRESHOLD_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_246    	0x00000000 // ZQ_CALSTART_TIMEOUT_F1:RW:16:16:=0x0000 ZQ_CS_HIGH_THRESHOLD_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_247    	0x00000000 // ZQ_CS_TIMEOUT_F1:RW:16:16:=0x0000 ZQ_CALLATCH_TIMEOUT_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_248    	0x00000000 // ZQ_CALSTART_NORM_THRESHOLD_F2:RW:16:16:=0x0000 ZQ_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_249    	0x00000000 // ZQ_CALLATCH_HIGH_THRESHOLD_F2:RW:16:16:=0x0000 ZQ_CALSTART_HIGH_THRESHOLD_F2:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_250    	0x00000000 // ZQ_CS_HIGH_THRESHOLD_F2:RW:16:16:=0x0000 ZQ_CS_NORM_THRESHOLD_F2:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_251    	0x00000000 // ZQ_CALLATCH_TIMEOUT_F2:RW:16:16:=0x0000 ZQ_CALSTART_TIMEOUT_F2:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_252    	0x00000000 // ZQ_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 ZQ_CS_TIMEOUT_F2:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_253    	0x00000000 // ZQ_CALSTART_HIGH_THRESHOLD_F3:RW:16:16:=0x0000 ZQ_CALSTART_NORM_THRESHOLD_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_254    	0x00000000 // ZQ_CS_NORM_THRESHOLD_F3:RW:16:16:=0x0000 ZQ_CALLATCH_HIGH_THRESHOLD_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_255    	0x00000000 // ZQ_CALSTART_TIMEOUT_F3:RW:16:16:=0x0000 ZQ_CS_HIGH_THRESHOLD_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_256    	0x00000000 // ZQ_CS_TIMEOUT_F3:RW:16:16:=0x0000 ZQ_CALLATCH_TIMEOUT_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_257    	0x00000000 // ZQ_CALSTART_NORM_THRESHOLD_F4:RW:16:16:=0x0000 ZQ_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_258    	0x00000000 // ZQ_CALLATCH_HIGH_THRESHOLD_F4:RW:16:16:=0x0000 ZQ_CALSTART_HIGH_THRESHOLD_F4:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_259    	0x00000000 // ZQ_CS_HIGH_THRESHOLD_F4:RW:16:16:=0x0000 ZQ_CS_NORM_THRESHOLD_F4:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_260    	0x00000000 // ZQ_CALLATCH_TIMEOUT_F4:RW:16:16:=0x0000 ZQ_CALSTART_TIMEOUT_F4:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_261    	0x00000000 // ZQ_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 ZQ_CS_TIMEOUT_F4:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_262    	0x00009903 // ZQINIT_F0:RW_D:8:12:=0x0099 RESERVED:RW:0:3:=0x03
    #define LP3_DENALI_CTL_DATA_263    	0x000E0038 // ZQCS_F0:RW:16:12:=0x000e ZQCL_F0:RW:0:12:=0x0038
    #define LP3_DENALI_CTL_DATA_264    	0x00000000 // TZQLAT_F0:RW:16:6:=0x00 TZQCAL_F0:RW:0:12:=0x0000
    #define LP3_DENALI_CTL_DATA_265    	0x00A601CC // ZQCL_F1:RW:16:12:=0x00a6 ZQINIT_F1:RW_D:0:12:=0x01cc
    #define LP3_DENALI_CTL_DATA_266    	0x0000002A // TZQCAL_F1:RW:16:12:=0x0000 ZQCS_F1:RW:0:12:=0x002a
    #define LP3_DENALI_CTL_DATA_267    	0x00026600 // ZQINIT_F2:RW_D:8:12:=0x0266 TZQLAT_F1:RW:0:6:=0x00
    #define LP3_DENALI_CTL_DATA_268    	0x003800DD // ZQCS_F2:RW:16:12:=0x0038 ZQCL_F2:RW:0:12:=0x00dd
    #define LP3_DENALI_CTL_DATA_269    	0x00000000 // TZQLAT_F2:RW:16:6:=0x00 TZQCAL_F2:RW:0:12:=0x0000
    #define LP3_DENALI_CTL_DATA_270    	0x014C0398 // ZQCL_F3:RW:16:12:=0x014c ZQINIT_F3:RW_D:0:12:=0x0398
    #define LP3_DENALI_CTL_DATA_271    	0x00000053 // TZQCAL_F3:RW:16:12:=0x0000 ZQCS_F3:RW:0:12:=0x0053
    #define LP3_DENALI_CTL_DATA_272    	0x00009900 // ZQINIT_F4:RW_D:8:12:=0x0099 TZQLAT_F3:RW:0:6:=0x00
    #define LP3_DENALI_CTL_DATA_273    	0x000E0038 // ZQCS_F4:RW:16:12:=0x000e ZQCL_F4:RW:0:12:=0x0038
    #define LP3_DENALI_CTL_DATA_274    	0x00000000 // ZQ_SW_REQ_START_LATCH_MAP:RW:24:2:=0x00 TZQLAT_F4:RW:16:6:=0x00 TZQCAL_F4:RW:0:12:=0x0000
    #define LP3_DENALI_CTL_DATA_275    	0x00080000 // ZQRESET_F0:RW:16:12:=0x0008 ZQ_REQ_PENDING:RD:8:1:=0x00 ZQ_REQ:WR:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_276    	0x001F0017 // ZQRESET_F2:RW:16:12:=0x001f ZQRESET_F1:RW:0:12:=0x0017
    #define LP3_DENALI_CTL_DATA_277    	0x0008002E // ZQRESET_F4:RW:16:12:=0x0008 ZQRESET_F3:RW:0:12:=0x002e
    #define LP3_DENALI_CTL_DATA_278    	0x01010100 // ZQ_CAL_LATCH_MAP_0:RW_D:24:2:=0x01 ZQ_CAL_START_MAP_0:RW_D:16:2:=0x01 ZQCS_ROTATE:RW:8:1:=0x01 NO_ZQ_INIT:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_279    	0x01000202 // ROW_DIFF:RW:24:3:=0x01 BANK_DIFF:RW:16:2:=0x00 ZQ_CAL_LATCH_MAP_1:RW_D:8:2:=0x02 ZQ_CAL_START_MAP_1:RW_D:0:2:=0x02
    #define LP3_DENALI_CTL_DATA_280    	0x0A000002 // APREBIT:RW_D:24:4:=0x0a BANK_ADDR_INTLV_EN:RW:16:1:=0x00 BANK_START_BIT:RW:8:5:=0x00 COL_DIFF:RW:0:4:=0x02
    #define LP3_DENALI_CTL_DATA_281    	0x0101FFFF // RESERVED:RW:24:1:=0x01 ADDR_CMP_EN:RW:16:1:=0x01 COMMAND_AGE_COUNT:RW:8:8:=0xff AGE_COUNT:RW:0:8:=0xff
    #define LP3_DENALI_CTL_DATA_282    	0x01010101 // RW_SAME_EN:RW:24:1:=0x01 PRIORITY_EN:RW:16:1:=0x01 PLACEMENT_EN:RW:8:1:=0x01 BANK_SPLIT_EN:RW:0:1:=0x01
    #define LP3_DENALI_CTL_DATA_283    	0x01010101 // DISABLE_RW_GROUP_W_BNK_CONFLICT:RW:24:2:=0x01 W2R_SPLIT_EN:RW:16:1:=0x01 CS_SAME_EN:RW:8:1:=0x01 RW_SAME_PAGE_EN:RW:0:1:=0x01
    #define LP3_DENALI_CTL_DATA_284    	0x0000011B // INHIBIT_DRAM_CMD:RW:24:2:=0x00 DISABLE_RD_INTERLEAVE:RW:16:1:=0x00 SWAP_EN:RW:8:1:=0x01 NUM_Q_ENTRIES_ACT_DISABLE:RW:0:5:=0x1b
    #define LP3_DENALI_CTL_DATA_285    	0x01000003 // RESERVED:RW:24:4:=0x01 MEMDATA_RATIO_0:RW:16:3:=0x00 REDUC:RW:8:1:=0x00 CS_MAP:RW:0:2:=0x03
    #define LP3_DENALI_CTL_DATA_286    	0x00000000 // MEMDATA_RATIO_1:RW:24:3:=0x00 RESERVED:RW:16:4:=0x00 RESERVED:RW:8:4:=0x00 RESERVED:RW:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_287    	0x00000001 // RESERVED:RW:24:4:=0x00 RESERVED:RW:16:4:=0x00 RESERVED:RW:8:4:=0x00 RESERVED:RW:0:4:=0x01
    #define LP3_DENALI_CTL_DATA_288    	0x00000000 // CONTROLLER_BUSY:RD:24:1:=0x00 WR_ORDER_REQ:RW:16:2:=0x00 IN_ORDER_ACCEPT:RW:8:1:=0x00 Q_FULLNESS:RW:0:5:=0x00
    #define LP3_DENALI_CTL_DATA_289    	0x01000100 // RD_PREAMBLE_TRAINING_EN:RW:24:1:=0x01 PREAMBLE_SUPPORT:RW:16:2:=0x00 CTRLUPD_REQ_PER_AREF_EN:RW:8:1:=0x01 CTRLUPD_REQ:WR:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_290    	0x00000000 // DFI_ERROR:RD:16:5:=0x00 RD_DBI_EN:RW:8:1:=0x00 WR_DBI_EN:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_291    	0x00000000 // RESERVED:RW+:24:1:=0x00 DFI_ERROR_INFO:RD:0:20:=0x000000
    #define LP3_DENALI_CTL_DATA_292    	0x00000000 // INT_STATUS:RD:0:39:=0x00000000
    #define LP3_DENALI_CTL_DATA_293    	0x00000000 // INT_STATUS:RD:0:39:=0x00
    #define LP3_DENALI_CTL_DATA_294    	0x00000000 // INT_ACK:WR:0:38:=0x00000000
    #define LP3_DENALI_CTL_DATA_295    	0x00000000 // INT_ACK:WR:0:38:=0x00
    #define LP3_DENALI_CTL_DATA_296    	0x00000000 // INT_MASK:RW:0:39:=0x00000000
    #define LP3_DENALI_CTL_DATA_297    	0x00000000 // INT_MASK:RW:0:39:=0x00
    #define LP3_DENALI_CTL_DATA_298    	0x00000000 // OUT_OF_RANGE_ADDR:RD:0:34:=0x00000000
    #define LP3_DENALI_CTL_DATA_299    	0x00000000 // OUT_OF_RANGE_TYPE:RD:24:7:=0x00 OUT_OF_RANGE_LENGTH:RD:8:12:=0x0000 OUT_OF_RANGE_ADDR:RD:0:34:=0x00
    #define LP3_DENALI_CTL_DATA_300    	0x00000000 // OUT_OF_RANGE_SOURCE_ID:RD:0:19:=0x000000
    #define LP3_DENALI_CTL_DATA_301    	0x00000000 // BIST_EXP_DATA:RD:0:128:=0x00000000
    #define LP3_DENALI_CTL_DATA_302    	0x00000000 // BIST_EXP_DATA:RD:0:128:=0x00000000
    #define LP3_DENALI_CTL_DATA_303    	0x00000000 // BIST_EXP_DATA:RD:0:128:=0x00000000
    #define LP3_DENALI_CTL_DATA_304    	0x00000000 // BIST_EXP_DATA:RD:0:128:=0x00000000
    #define LP3_DENALI_CTL_DATA_305    	0x00000000 // BIST_FAIL_DATA:RD:0:128:=0x00000000
    #define LP3_DENALI_CTL_DATA_306    	0x00000000 // BIST_FAIL_DATA:RD:0:128:=0x00000000
    #define LP3_DENALI_CTL_DATA_307    	0x00000000 // BIST_FAIL_DATA:RD:0:128:=0x00000000
    #define LP3_DENALI_CTL_DATA_308    	0x00000000 // BIST_FAIL_DATA:RD:0:128:=0x00000000
    #define LP3_DENALI_CTL_DATA_309    	0x00000000 // BIST_FAIL_ADDR:RD:0:34:=0x00000000
    #define LP3_DENALI_CTL_DATA_310    	0x00000000 // BIST_FAIL_ADDR:RD:0:34:=0x00
    #define LP3_DENALI_CTL_DATA_311    	0x00000000 // PORT_CMD_ERROR_ADDR:RD:0:34:=0x00000000
    #define LP3_DENALI_CTL_DATA_312    	0x00000000 // PORT_CMD_ERROR_ID:RD:8:19:=0x000000 PORT_CMD_ERROR_ADDR:RD:0:34:=0x00
    #define LP3_DENALI_CTL_DATA_313    	0x02010100 // ODT_RD_MAP_CS1:RW:24:2:=0x02 ODT_WR_MAP_CS0:RW:16:2:=0x01 ODT_RD_MAP_CS0:RW:8:2:=0x01 PORT_CMD_ERROR_TYPE:RD:0:2:=0x00
    #define LP3_DENALI_CTL_DATA_314    	0x03020102 // TODTL_2CMD_F2:RW:24:8:=0x03 TODTL_2CMD_F1:RW:16:8:=0x02 TODTL_2CMD_F0:RW:8:8:=0x01 ODT_WR_MAP_CS1:RW:0:2:=0x02
    #define LP3_DENALI_CTL_DATA_315    	0x07070104 // TODTH_RD:RW:24:4:=0x07 TODTH_WR:RW:16:4:=0x07 TODTL_2CMD_F4:RW:8:8:=0x01 TODTL_2CMD_F3:RW:0:8:=0x04
    #define LP3_DENALI_CTL_DATA_316    	0x01010101 // ODT_EN_F3:RW:24:1:=0x01 ODT_EN_F2:RW:16:1:=0x01 ODT_EN_F1:RW:8:1:=0x01 ODT_EN_F0:RW:0:1:=0x01
    #define LP3_DENALI_CTL_DATA_317    	0x02020101 // WR_TO_ODTH_F1:RW:24:6:=0x02 WR_TO_ODTH_F0:RW:16:6:=0x02 EN_ODT_ASSERT_EXCEPT_RD:RW:8:1:=0x01 ODT_EN_F4:RW:0:1:=0x01
    #define LP3_DENALI_CTL_DATA_318    	0x05020403 // RD_TO_ODTH_F0:RW:24:6:=0x05 WR_TO_ODTH_F4:RW:16:6:=0x02 WR_TO_ODTH_F3:RW:8:6:=0x04 WR_TO_ODTH_F2:RW:0:6:=0x03
    #define LP3_DENALI_CTL_DATA_319    	0x050C0807 // RD_TO_ODTH_F4:RW:24:6:=0x05 RD_TO_ODTH_F3:RW:16:6:=0x0c RD_TO_ODTH_F2:RW:8:6:=0x08 RD_TO_ODTH_F1:RW:0:6:=0x07
    #define LP3_DENALI_CTL_DATA_320    	0x08080808 // RW2MRW_DLY_F3:RW_D:24:4:=0x08 RW2MRW_DLY_F2:RW_D:16:4:=0x08 RW2MRW_DLY_F1:RW_D:8:4:=0x08 RW2MRW_DLY_F0:RW_D:0:4:=0x08
    #define LP3_DENALI_CTL_DATA_321    	0x02020208 // W2R_DIFFCS_DLY_F0:RW_D:24:5:=0x02 R2W_DIFFCS_DLY_F0:RW_D:16:5:=0x02 R2R_DIFFCS_DLY_F0:RW_D:8:5:=0x02 RW2MRW_DLY_F4:RW_D:0:4:=0x08
    #define LP3_DENALI_CTL_DATA_322    	0x01020201 // W2R_DIFFCS_DLY_F1:RW_D:24:5:=0x01 R2W_DIFFCS_DLY_F1:RW_D:16:5:=0x02 R2R_DIFFCS_DLY_F1:RW_D:8:5:=0x02 W2W_DIFFCS_DLY_F0:RW_D:0:5:=0x01
    #define LP3_DENALI_CTL_DATA_323    	0x03030201 // W2R_DIFFCS_DLY_F2:RW_D:24:5:=0x03 R2W_DIFFCS_DLY_F2:RW_D:16:5:=0x03 R2R_DIFFCS_DLY_F2:RW_D:8:5:=0x02 W2W_DIFFCS_DLY_F1:RW_D:0:5:=0x01
    #define LP3_DENALI_CTL_DATA_324    	0x01030201 // W2R_DIFFCS_DLY_F3:RW_D:24:5:=0x01 R2W_DIFFCS_DLY_F3:RW_D:16:5:=0x03 R2R_DIFFCS_DLY_F3:RW_D:8:5:=0x02 W2W_DIFFCS_DLY_F2:RW_D:0:5:=0x01
    #define LP3_DENALI_CTL_DATA_325    	0x02020201 // W2R_DIFFCS_DLY_F4:RW_D:24:5:=0x02 R2W_DIFFCS_DLY_F4:RW_D:16:5:=0x02 R2R_DIFFCS_DLY_F4:RW_D:8:5:=0x02 W2W_DIFFCS_DLY_F3:RW_D:0:5:=0x01
    #define LP3_DENALI_CTL_DATA_326    	0x02020001 // R2W_SAMECS_DLY_F1:RW_D:24:5:=0x02 R2W_SAMECS_DLY_F0:RW_D:16:5:=0x02 R2R_SAMECS_DLY:RW:8:5:=0x00 W2W_DIFFCS_DLY_F4:RW_D:0:5:=0x01
    #define LP3_DENALI_CTL_DATA_327    	0x00020202 // W2R_SAMECS_DLY:RW:24:5:=0x00 R2W_SAMECS_DLY_F4:RW_D:16:5:=0x02 R2W_SAMECS_DLY_F3:RW_D:8:5:=0x02 R2W_SAMECS_DLY_F2:RW_D:0:5:=0x02
    #define LP3_DENALI_CTL_DATA_328    	0x03010100 // TDQSCK_MAX_F1:RW:24:4:=0x03 TDQSCK_MIN_F0:RW:16:2:=0x01 TDQSCK_MAX_F0:RW:8:4:=0x01 W2W_SAMECS_DLY:RW:0:5:=0x00
    #define LP3_DENALI_CTL_DATA_329    	0x06020402 // TDQSCK_MAX_F3:RW:24:4:=0x06 TDQSCK_MIN_F2:RW:16:2:=0x02 TDQSCK_MAX_F2:RW:8:4:=0x04 TDQSCK_MIN_F1:RW:0:2:=0x02
    #define LP3_DENALI_CTL_DATA_330    	0x00010103 // SW_LEVELING_MODE:RW:24:3:=0x00 TDQSCK_MIN_F4:RW:16:2:=0x01 TDQSCK_MAX_F4:RW:8:4:=0x01 TDQSCK_MIN_F3:RW:0:2:=0x03
    #define LP3_DENALI_CTL_DATA_331    	0x00000000 // SWLVL_OP_DONE:RD:24:1:=0x00 SWLVL_EXIT:WR:16:1:=0x00 SWLVL_START:WR:8:1:=0x00 SWLVL_LOAD:WR:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_332    	0x00000000 // SWLVL_RESP_3:RD:24:1:=0x00 SWLVL_RESP_2:RD:16:1:=0x00 SWLVL_RESP_1:RD:8:1:=0x00 SWLVL_RESP_0:RD:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_333    	0x0D000001 // WLDQSEN:RW:24:6:=0x0d WRLVL_CS:RW:16:1:=0x00 WRLVL_REQ:WR:8:1:=0x00 PHYUPD_APPEND_EN:RW:0:1:=0x01
    #define LP3_DENALI_CTL_DATA_334    	0x00010028 // WRLVL_PERIODIC:RW:24:1:=0x00 DFI_PHY_WRLVL_MODE:RW:16:1:=0x01 WRLVL_EN:RW:8:1:=0x00 WLMRD:RW:0:6:=0x28
    #define LP3_DENALI_CTL_DATA_335    	0x00010000 // WRLVL_ROTATE:RW:24:1:=0x00 WRLVL_AREF_EN:RW:16:1:=0x01 WRLVL_RESP_MASK:RW:8:4:=0x00 WRLVL_ON_SREF_EXIT:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_336    	0x00000003 // WRLVL_NORM_THRESHOLD_F0:RW:16:16:=0x0000 WRLVL_ERROR_STATUS:RD:8:2:=0x00 WRLVL_CS_MAP:RW:0:2:=0x03
    #define LP3_DENALI_CTL_DATA_337    	0x00000000 // WRLVL_TIMEOUT_F0:RW:16:16:=0x0000 WRLVL_HIGH_THRESHOLD_F0:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_338    	0x00000000 // WRLVL_DFI_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 WRLVL_SW_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_339    	0x00000000 // WRLVL_HIGH_THRESHOLD_F1:RW:16:16:=0x0000 WRLVL_NORM_THRESHOLD_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_340    	0x00000000 // WRLVL_SW_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 WRLVL_TIMEOUT_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_341    	0x00000000 // WRLVL_NORM_THRESHOLD_F2:RW:16:16:=0x0000 WRLVL_DFI_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_342    	0x00000000 // WRLVL_TIMEOUT_F2:RW:16:16:=0x0000 WRLVL_HIGH_THRESHOLD_F2:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_343    	0x00000000 // WRLVL_DFI_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 WRLVL_SW_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_344    	0x00000000 // WRLVL_HIGH_THRESHOLD_F3:RW:16:16:=0x0000 WRLVL_NORM_THRESHOLD_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_345    	0x00000000 // WRLVL_SW_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 WRLVL_TIMEOUT_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_346    	0x00000000 // WRLVL_NORM_THRESHOLD_F4:RW:16:16:=0x0000 WRLVL_DFI_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_347    	0x00000000 // WRLVL_TIMEOUT_F4:RW:16:16:=0x0000 WRLVL_HIGH_THRESHOLD_F4:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_348    	0x00000000 // WRLVL_DFI_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 WRLVL_SW_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_349    	0x00000000 // RDLVL_SEQ_EN:RW:24:4:=0x00 RDLVL_CS:RW:16:1:=0x00 RDLVL_GATE_REQ:WR:8:1:=0x00 RDLVL_REQ:WR:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_350    	0x00010100 // RDLVL_PERIODIC:RW:24:1:=0x00 DFI_PHY_RDLVL_GATE_MODE:RW:16:1:=0x01 DFI_PHY_RDLVL_MODE:RW:8:1:=0x01 RDLVL_GATE_SEQ_EN:RW:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_351    	0x01000000 // RDLVL_AREF_EN:RW:24:1:=0x01 RDLVL_GATE_ON_SREF_EXIT:RW:16:1:=0x00 RDLVL_GATE_PERIODIC:RW:8:1:=0x00 RDLVL_ON_SREF_EXIT:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_352    	0x00000001 // RDLVL_GATE_ROTATE:RW:24:1:=0x00 RDLVL_ROTATE:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RDLVL_GATE_AREF_EN:RW:0:1:=0x01
    #define LP3_DENALI_CTL_DATA_353    	0x00000303 // RDLVL_NORM_THRESHOLD_F0:RW:16:16:=0x0000 RDLVL_GATE_CS_MAP:RW:8:2:=0x03 RDLVL_CS_MAP:RW:0:2:=0x03
    #define LP3_DENALI_CTL_DATA_354    	0x00000000 // RDLVL_TIMEOUT_F0:RW:16:16:=0x0000 RDLVL_HIGH_THRESHOLD_F0:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_355    	0x00000000 // RDLVL_DFI_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 RDLVL_SW_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_356    	0x00000000 // RDLVL_GATE_HIGH_THRESHOLD_F0:RW:16:16:=0x0000 RDLVL_GATE_NORM_THRESHOLD_F0:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_357    	0x00000000 // RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 RDLVL_GATE_TIMEOUT_F0:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_358    	0x00000000 // RDLVL_NORM_THRESHOLD_F1:RW:16:16:=0x0000 RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_359    	0x00000000 // RDLVL_TIMEOUT_F1:RW:16:16:=0x0000 RDLVL_HIGH_THRESHOLD_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_360    	0x00000000 // RDLVL_DFI_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 RDLVL_SW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_361    	0x00000000 // RDLVL_GATE_HIGH_THRESHOLD_F1:RW:16:16:=0x0000 RDLVL_GATE_NORM_THRESHOLD_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_362    	0x00000000 // RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 RDLVL_GATE_TIMEOUT_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_363    	0x00000000 // RDLVL_NORM_THRESHOLD_F2:RW:16:16:=0x0000 RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_364    	0x00000000 // RDLVL_TIMEOUT_F2:RW:16:16:=0x0000 RDLVL_HIGH_THRESHOLD_F2:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_365    	0x00000000 // RDLVL_DFI_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 RDLVL_SW_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_366    	0x00000000 // RDLVL_GATE_HIGH_THRESHOLD_F2:RW:16:16:=0x0000 RDLVL_GATE_NORM_THRESHOLD_F2:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_367    	0x00000000 // RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 RDLVL_GATE_TIMEOUT_F2:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_368    	0x00000000 // RDLVL_NORM_THRESHOLD_F3:RW:16:16:=0x0000 RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_369    	0x00000000 // RDLVL_TIMEOUT_F3:RW:16:16:=0x0000 RDLVL_HIGH_THRESHOLD_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_370    	0x00000000 // RDLVL_DFI_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 RDLVL_SW_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_371    	0x00000000 // RDLVL_GATE_HIGH_THRESHOLD_F3:RW:16:16:=0x0000 RDLVL_GATE_NORM_THRESHOLD_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_372    	0x00000000 // RDLVL_GATE_SW_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 RDLVL_GATE_TIMEOUT_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_373    	0x00000000 // RDLVL_NORM_THRESHOLD_F4:RW:16:16:=0x0000 RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_374    	0x00000000 // RDLVL_TIMEOUT_F4:RW:16:16:=0x0000 RDLVL_HIGH_THRESHOLD_F4:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_375    	0x00000000 // RDLVL_DFI_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 RDLVL_SW_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_376    	0x00000000 // RDLVL_GATE_HIGH_THRESHOLD_F4:RW:16:16:=0x0000 RDLVL_GATE_NORM_THRESHOLD_F4:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_377    	0x00000000 // RDLVL_GATE_SW_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 RDLVL_GATE_TIMEOUT_F4:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_378    	0x00000000 // CALVL_CS:RW:24:1:=0x00 CALVL_REQ:WR:16:1:=0x00 RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_379    	0x000556AA // CALVL_PAT_0:RW:0:20:=0x0556aa
    #define LP3_DENALI_CTL_DATA_380    	0x000AAAAA // CALVL_BG_PAT_0:RW:0:20:=0x0aaaaa
    #define LP3_DENALI_CTL_DATA_381    	0x000AA955 // CALVL_PAT_1:RW:0:20:=0x0aa955
    #define LP3_DENALI_CTL_DATA_382    	0x00055555 // CALVL_BG_PAT_1:RW:0:20:=0x055555
    #define LP3_DENALI_CTL_DATA_383    	0x000B3133 // CALVL_PAT_2:RW:0:20:=0x0b3133
    #define LP3_DENALI_CTL_DATA_384    	0x0004CD33 // CALVL_BG_PAT_2:RW:0:20:=0x04cd33
    #define LP3_DENALI_CTL_DATA_385    	0x0004CECC // CALVL_PAT_3:RW:0:20:=0x04cecc
    #define LP3_DENALI_CTL_DATA_386    	0x000B32CC // RESERVED:RW:24:1:=0x00 CALVL_BG_PAT_3:RW:0:20:=0x0b32cc
    #define LP3_DENALI_CTL_DATA_387    	0x00010300 // CALVL_PERIODIC:RW:24:1:=0x00 DFI_PHY_CALVL_MODE:RW:16:1:=0x01 CALVL_SEQ_EN:RW:8:2:=0x03 RESERVED:RW:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_388    	0x03000100 // CALVL_CS_MAP:RW:24:2:=0x03 CALVL_ROTATE:RW:16:1:=0x00 CALVL_AREF_EN:RW:8:1:=0x01 CALVL_ON_SREF_EXIT:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_389    	0x00000000 // CALVL_HIGH_THRESHOLD_F0:RW:16:16:=0x0000 CALVL_NORM_THRESHOLD_F0:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_390    	0x00000000 // CALVL_SW_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 CALVL_TIMEOUT_F0:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_391    	0x00000000 // CALVL_NORM_THRESHOLD_F1:RW:16:16:=0x0000 CALVL_DFI_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_392    	0x00000000 // CALVL_TIMEOUT_F1:RW:16:16:=0x0000 CALVL_HIGH_THRESHOLD_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_393    	0x00000000 // CALVL_DFI_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 CALVL_SW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_394    	0x00000000 // CALVL_HIGH_THRESHOLD_F2:RW:16:16:=0x0000 CALVL_NORM_THRESHOLD_F2:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_395    	0x00000000 // CALVL_SW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 CALVL_TIMEOUT_F2:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_396    	0x00000000 // CALVL_NORM_THRESHOLD_F3:RW:16:16:=0x0000 CALVL_DFI_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_397    	0x00000000 // CALVL_TIMEOUT_F3:RW:16:16:=0x0000 CALVL_HIGH_THRESHOLD_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_398    	0x00000000 // CALVL_DFI_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 CALVL_SW_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_399    	0x00000000 // CALVL_HIGH_THRESHOLD_F4:RW:16:16:=0x0000 CALVL_NORM_THRESHOLD_F4:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_400    	0x00000000 // CALVL_SW_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 CALVL_TIMEOUT_F4:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_401    	0x00000000 // AXI0_FIXED_PORT_PRIORITY_ENABLE:RW:24:1:=0x00 AXI0_ALL_STROBES_USED_ENABLE:RW:16:1:=0x00 CALVL_DFI_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
    #define LP3_DENALI_CTL_DATA_402    	0x00000303 // AXI1_ALL_STROBES_USED_ENABLE:RW:24:1:=0x00 AXI0_FIFO_TYPE_REG:RW:16:2:=0x00 AXI0_W_PRIORITY:RW:8:4:=0x03 AXI0_R_PRIORITY:RW:0:4:=0x03
    #define LP3_DENALI_CTL_DATA_403    	0x00030300 // AXI1_FIFO_TYPE_REG:RW:24:2:=0x00 AXI1_W_PRIORITY:RW:16:4:=0x03 AXI1_R_PRIORITY:RW:8:4:=0x03 AXI1_FIXED_PORT_PRIORITY_ENABLE:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_404    	0x03030000 // AXI2_W_PRIORITY:RW:24:4:=0x03 AXI2_R_PRIORITY:RW:16:4:=0x03 AXI2_FIXED_PORT_PRIORITY_ENABLE:RW:8:1:=0x00 AXI2_ALL_STROBES_USED_ENABLE:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_405    	0x03000000 // AXI3_R_PRIORITY:RW:24:4:=0x03 AXI3_FIXED_PORT_PRIORITY_ENABLE:RW:16:1:=0x00 AXI3_ALL_STROBES_USED_ENABLE:RW:8:1:=0x00 AXI2_FIFO_TYPE_REG:RW:0:2:=0x00
    #define LP3_DENALI_CTL_DATA_406    	0x00000003 // AXI4_FIXED_PORT_PRIORITY_ENABLE:RW:24:1:=0x00 AXI4_ALL_STROBES_USED_ENABLE:RW:16:1:=0x00 AXI3_FIFO_TYPE_REG:RW:8:2:=0x00 AXI3_W_PRIORITY:RW:0:4:=0x03
    #define LP3_DENALI_CTL_DATA_407    	0x00000303 // AXI5_ALL_STROBES_USED_ENABLE:RW:24:1:=0x00 AXI4_FIFO_TYPE_REG:RW:16:2:=0x00 AXI4_W_PRIORITY:RW:8:4:=0x03 AXI4_R_PRIORITY:RW:0:4:=0x03
    #define LP3_DENALI_CTL_DATA_408    	0x00030300 // AXI5_FIFO_TYPE_REG:RW:24:2:=0x00 AXI5_W_PRIORITY:RW:16:4:=0x03 AXI5_R_PRIORITY:RW:8:4:=0x03 AXI5_FIXED_PORT_PRIORITY_ENABLE:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_409    	0x0001210F // AXI0_CURRENT_BDW:RD:24:7:=0x00 AXI0_BDW_OVFLOW:RW:16:1:=0x01 AXI0_BDW:RW:8:7:=0x21 ARB_CMD_Q_THRESHOLD:RW:0:5:=0x0f
    #define LP3_DENALI_CTL_DATA_410    	0x21000121 // AXI2_BDW:RW:24:7:=0x21 AXI1_CURRENT_BDW:RD:16:7:=0x00 AXI1_BDW_OVFLOW:RW:8:1:=0x01 AXI1_BDW:RW:0:7:=0x21
    #define LP3_DENALI_CTL_DATA_411    	0x01210001 // AXI3_BDW_OVFLOW:RW:24:1:=0x01 AXI3_BDW:RW:16:7:=0x21 AXI2_CURRENT_BDW:RD:8:7:=0x00 AXI2_BDW_OVFLOW:RW:0:1:=0x01
    #define LP3_DENALI_CTL_DATA_412    	0x00012100 // AXI4_CURRENT_BDW:RD:24:7:=0x00 AXI4_BDW_OVFLOW:RW:16:1:=0x01 AXI4_BDW:RW:8:7:=0x21 AXI3_CURRENT_BDW:RD:0:7:=0x00
    #define LP3_DENALI_CTL_DATA_413    	0x00000121 // CKE_STATUS:RD:24:2:=0x00 AXI5_CURRENT_BDW:RD:16:7:=0x00 AXI5_BDW_OVFLOW:RW:8:1:=0x01 AXI5_BDW:RW:0:7:=0x21
    #define LP3_DENALI_CTL_DATA_414    	0x00000000 // DLL_RST_ADJ_DLY:RW:24:8:=0x00 DLL_RST_DELAY:RW:8:16:=0x0000 MEM_RST_VALID:RD:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_415    	0x1C160000 // TDFI_PHY_RDLAT_F1:RW_D:24:7:=0x1c TDFI_PHY_RDLAT_F0:RW_D:16:7:=0x16 UPDATE_ERROR_STATUS:RD:8:7:=0x00 TDFI_PHY_WRLAT:RD:0:7:=0x00
    #define LP3_DENALI_CTL_DATA_416    	0x0016251F // TDFI_RDDATA_EN:RD:24:7:=0x00 TDFI_PHY_RDLAT_F4:RW_D:16:7:=0x16 TDFI_PHY_RDLAT_F3:RW_D:8:7:=0x25 TDFI_PHY_RDLAT_F2:RW_D:0:7:=0x1f
    #define LP3_DENALI_CTL_DATA_417    	0x04980800 // TDFI_CTRLUPD_MAX_F0:RW:16:16:=0x0498 TDFI_CTRLUPD_MIN:RW:8:4:=0x08 DRAM_CLK_DISABLE:RW:0:2:=0x00
    #define LP3_DENALI_CTL_DATA_418    	0x00000200 // TDFI_PHYUPD_TYPE0_F0:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_419    	0x00000200 // TDFI_PHYUPD_TYPE1_F0:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_420    	0x00000200 // TDFI_PHYUPD_TYPE2_F0:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_421    	0x00000200 // TDFI_PHYUPD_TYPE3_F0:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_422    	0x00000498 // TDFI_PHYUPD_RESP_F0:RW:0:16:=0x0498
    #define LP3_DENALI_CTL_DATA_423    	0x00002DF0 // TDFI_CTRLUPD_INTERVAL_F0:RW:0:32:=0x00002df0
    #define LP3_DENALI_CTL_DATA_424    	0x0DF20205 // TDFI_CTRLUPD_MAX_F1:RW:16:16:=0x0df2 WRLAT_ADJ_F0:RW:8:7:=0x02 RDLAT_ADJ_F0:RW:0:7:=0x05
    #define LP3_DENALI_CTL_DATA_425    	0x00000200 // TDFI_PHYUPD_TYPE0_F1:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_426    	0x00000200 // TDFI_PHYUPD_TYPE1_F1:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_427    	0x00000200 // TDFI_PHYUPD_TYPE2_F1:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_428    	0x00000200 // TDFI_PHYUPD_TYPE3_F1:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_429    	0x00000DF2 // TDFI_PHYUPD_RESP_F1:RW:0:16:=0x0df2
    #define LP3_DENALI_CTL_DATA_430    	0x00008B74 // TDFI_CTRLUPD_INTERVAL_F1:RW:0:32:=0x00008b74
    #define LP3_DENALI_CTL_DATA_431    	0x129E0305 // TDFI_CTRLUPD_MAX_F2:RW:16:16:=0x129e WRLAT_ADJ_F1:RW:8:7:=0x03 RDLAT_ADJ_F1:RW:0:7:=0x05
    #define LP3_DENALI_CTL_DATA_432    	0x00000200 // TDFI_PHYUPD_TYPE0_F2:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_433    	0x00000200 // TDFI_PHYUPD_TYPE1_F2:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_434    	0x00000200 // TDFI_PHYUPD_TYPE2_F2:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_435    	0x00000200 // TDFI_PHYUPD_TYPE3_F2:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_436    	0x0000129E // TDFI_PHYUPD_RESP_F2:RW:0:16:=0x129e
    #define LP3_DENALI_CTL_DATA_437    	0x0000BA2C // TDFI_CTRLUPD_INTERVAL_F2:RW:0:32:=0x0000ba2c
    #define LP3_DENALI_CTL_DATA_438    	0x1BF60506 // TDFI_CTRLUPD_MAX_F3:RW:16:16:=0x1bf6 WRLAT_ADJ_F2:RW:8:7:=0x05 RDLAT_ADJ_F2:RW:0:7:=0x06
    #define LP3_DENALI_CTL_DATA_439    	0x00000200 // TDFI_PHYUPD_TYPE0_F3:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_440    	0x00000200 // TDFI_PHYUPD_TYPE1_F3:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_441    	0x00000200 // TDFI_PHYUPD_TYPE2_F3:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_442    	0x00000200 // TDFI_PHYUPD_TYPE3_F3:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_443    	0x00001BF6 // TDFI_PHYUPD_RESP_F3:RW:0:16:=0x1bf6
    #define LP3_DENALI_CTL_DATA_444    	0x0001179C // TDFI_CTRLUPD_INTERVAL_F3:RW:0:32:=0x0001179c
    #define LP3_DENALI_CTL_DATA_445    	0x04980708 // TDFI_CTRLUPD_MAX_F4:RW:16:16:=0x0498 WRLAT_ADJ_F3:RW:8:7:=0x07 RDLAT_ADJ_F3:RW:0:7:=0x08
    #define LP3_DENALI_CTL_DATA_446    	0x00000200 // TDFI_PHYUPD_TYPE0_F4:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_447    	0x00000200 // TDFI_PHYUPD_TYPE1_F4:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_448    	0x00000200 // TDFI_PHYUPD_TYPE2_F4:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_449    	0x00000200 // TDFI_PHYUPD_TYPE3_F4:RW:0:32:=0x00000200
    #define LP3_DENALI_CTL_DATA_450    	0x00000498 // TDFI_PHYUPD_RESP_F4:RW:0:16:=0x0498
    #define LP3_DENALI_CTL_DATA_451    	0x00002DF0 // TDFI_CTRLUPD_INTERVAL_F4:RW:0:32:=0x00002df0
    #define LP3_DENALI_CTL_DATA_452    	0x02020205 // TDFI_CTRL_DELAY_F1:RW_D:24:4:=0x02 TDFI_CTRL_DELAY_F0:RW_D:16:4:=0x02 WRLAT_ADJ_F4:RW:8:7:=0x02 RDLAT_ADJ_F4:RW:0:7:=0x05
    #define LP3_DENALI_CTL_DATA_453    	0x02020202 // TDFI_DRAM_CLK_DISABLE:RW:24:4:=0x02 TDFI_CTRL_DELAY_F4:RW_D:16:4:=0x02 TDFI_CTRL_DELAY_F3:RW_D:8:4:=0x02 TDFI_CTRL_DELAY_F2:RW_D:0:4:=0x02
    #define LP3_DENALI_CTL_DATA_454    	0x00180303 // TDFI_WRLVL_WW:RW:16:10:=0x0018 TDFI_WRLVL_EN:RW:8:8:=0x03 TDFI_DRAM_CLK_ENABLE:RW:0:4:=0x03
    #define LP3_DENALI_CTL_DATA_455    	0x00000000 // TDFI_WRLVL_RESP:RW:0:32:=0x00000000
    #define LP3_DENALI_CTL_DATA_456    	0x00000000 // TDFI_WRLVL_MAX:RW:0:32:=0x00000000
    #define LP3_DENALI_CTL_DATA_457    	0x00001403 // TDFI_RDLVL_RR:RW:8:10:=0x0014 TDFI_RDLVL_EN:RW:0:8:=0x03
    #define LP3_DENALI_CTL_DATA_458    	0x00000000 // TDFI_RDLVL_RESP:RW:0:32:=0x00000000
    #define LP3_DENALI_CTL_DATA_459    	0x00000000 // RDLVL_GATE_EN:RW:16:1:=0x00 RDLVL_EN:RW:8:1:=0x00 RDLVL_RESP_MASK:RW:0:8:=0x00
    #define LP3_DENALI_CTL_DATA_460    	0x00000000 // TDFI_RDLVL_MAX:RW:0:32:=0x00000000
    #define LP3_DENALI_CTL_DATA_461    	0x00030000 // TDFI_CALVL_EN:RW:16:8:=0x03 RDLVL_GATE_ERROR_STATUS:RD:8:2:=0x00 RDLVL_ERROR_STATUS:RD:0:2:=0x00
    #define LP3_DENALI_CTL_DATA_462    	0x0008001A // TDFI_CALVL_CAPTURE_F0:RW:16:10:=0x0008 TDFI_CALVL_CC_F0:RW:0:10:=0x001a
    #define LP3_DENALI_CTL_DATA_463    	0x000B001D // TDFI_CALVL_CAPTURE_F1:RW:16:10:=0x000b TDFI_CALVL_CC_F1:RW:0:10:=0x001d
    #define LP3_DENALI_CTL_DATA_464    	0x000C001E // TDFI_CALVL_CAPTURE_F2:RW:16:10:=0x000c TDFI_CALVL_CC_F2:RW:0:10:=0x001e
    #define LP3_DENALI_CTL_DATA_465    	0x000F0021 // TDFI_CALVL_CAPTURE_F3:RW:16:10:=0x000f TDFI_CALVL_CC_F3:RW:0:10:=0x0021
    #define LP3_DENALI_CTL_DATA_466    	0x0008001A // TDFI_CALVL_CAPTURE_F4:RW:16:10:=0x0008 TDFI_CALVL_CC_F4:RW:0:10:=0x001a
    #define LP3_DENALI_CTL_DATA_467    	0x00000000 // TDFI_CALVL_RESP:RW:0:32:=0x00000000
    #define LP3_DENALI_CTL_DATA_468    	0x00000000 // TDFI_CALVL_MAX:RW:0:32:=0x00000000
    #define LP3_DENALI_CTL_DATA_469    	0x01000000 // TDFI_PHY_WRDATA:RW:24:3:=0x01 CALVL_ERROR_STATUS:RD:16:4:=0x00 CALVL_EN:RW:8:1:=0x00 CALVL_RESP_MASK:RW:0:1:=0x00
    #define LP3_DENALI_CTL_DATA_470    	0x02030101 // TDFI_WRCSLAT_F1:RW:24:7:=0x02 TDFI_RDCSLAT_F1:RW:16:7:=0x03 TDFI_WRCSLAT_F0:RW:8:7:=0x01 TDFI_RDCSLAT_F0:RW:0:7:=0x01
    #define LP3_DENALI_CTL_DATA_471    	0x02090005 // TDFI_WRCSLAT_F3:RW:24:7:=0x02 TDFI_RDCSLAT_F3:RW:16:7:=0x09 TDFI_WRCSLAT_F2:RW:8:7:=0x00 TDFI_RDCSLAT_F2:RW:0:7:=0x05
    #define LP3_DENALI_CTL_DATA_472    	0x01050101 // EN_1T_TIMING:RW:24:1:=0x01 TDFI_WRDATA_DELAY:RW:16:8:=0x05 TDFI_WRCSLAT_F4:RW:8:7:=0x01 TDFI_RDCSLAT_F4:RW:0:7:=0x01
    #define LP3_DENALI_CTL_DATA_473    	0x01010001 // RESERVED:RW_D:24:3:=0x01 MULTI_CHANNEL_ZQ_CAL_MASTER:RW_D:16:1:=0x01 BL_ON_FLY_ENABLE:RW_D:8:1:=0x00 DISABLE_MEMORY_MASKED_WRITE:RW_D:0:1:=0x01
    #define LP3_DENALI_CTL_DATA_474    	0x01010101 // RESERVED:RW_D:24:3:=0x01 RESERVED:RW_D:16:3:=0x01 RESERVED:RW_D:8:3:=0x01 RESERVED:RW_D:0:3:=0x01
    #define LP3_DENALI_CTL_DATA_475    	0x00010001 // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x01 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:3:=0x01
    #define LP3_DENALI_CTL_DATA_476    	0x01010001 // RESERVED:RW_D:24:4:=0x01 RESERVED:RW_D:16:4:=0x01 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x01
    #define LP3_DENALI_CTL_DATA_477    	0x02000100 // RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x01 RESERVED:RW_D:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_478    	0x00000100 // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x01 RESERVED:RW_D:0:4:=0x00
    #define LP3_DENALI_CTL_DATA_479    	0x02000201 // RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x01
    #define LP3_DENALI_CTL_DATA_480    	0x00000000 // RESERVED:RW_D:0:4:=0x00
    //}}}
#else
    //{{{
    #define LP3_DENALI_CTL_DATA_0	0x00000700 // VERSION:RD:16:16:=0x0000 DRAM_CLASS:RW:8:4:=0x07 START:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_1	0x00000000 // READ_DATA_FIFO_DEPTH:RD:24:8:=0x00 MAX_CS_REG:RD:16:2:=0x00 MAX_COL_REG:RD:8:4:=0x00 MAX_ROW_REG:RD:0:5:=0x00
#define LP3_DENALI_CTL_DATA_2	0x00000000 // MEMCD_RMODW_FIFO_DEPTH:RD:24:8:=0x00 WRITE_DATA_FIFO_PTR_WIDTH:RD:16:8:=0x00 WRITE_DATA_FIFO_DEPTH:RD:8:8:=0x00 READ_DATA_FIFO_PTR_WIDTH:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_3	0x00000000 // AXI0_RDFIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI0_CMDFIFO_LOG2_DEPTH:RD:16:8:=0x00 ASYNC_CDC_STAGES:RD:8:8:=0x00 MEMCD_RMODW_FIFO_PTR_WIDTH:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_4	0x00000000 // AXI1_CMDFIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI0_TRANS_WRFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI0_WR_ARRAY_LOG2_DEPTH:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_5	0x00000000 // AXI1_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI1_TRANS_WRFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI1_WR_ARRAY_LOG2_DEPTH:RD:8:8:=0x00 AXI1_RDFIFO_LOG2_DEPTH:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_6	0x00000000 // AXI2_TRANS_WRFIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI2_WR_ARRAY_LOG2_DEPTH:RD:16:8:=0x00 AXI2_RDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI2_CMDFIFO_LOG2_DEPTH:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_7	0x00000000 // AXI3_WR_ARRAY_LOG2_DEPTH:RD:24:8:=0x00 AXI3_RDFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI3_CMDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI2_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_8	0x00000000 // AXI4_RDFIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI4_CMDFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI3_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI3_TRANS_WRFIFO_LOG2_DEPTH:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_9	0x00000000 // AXI5_CMDFIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI4_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI4_TRANS_WRFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI4_WR_ARRAY_LOG2_DEPTH:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_10	0x00000000 // AXI5_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI5_TRANS_WRFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI5_WR_ARRAY_LOG2_DEPTH:RD:8:8:=0x00 AXI5_RDFIFO_LOG2_DEPTH:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_11	0x00001800 // TINIT_F0:RW:8:24:=0x000018 DFS_CLOSE_BANKS:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_12	0x0000B648 // TINIT3_F0:RW:0:24:=0x00b648
#define LP3_DENALI_CTL_DATA_13	0x000000EA // TINIT4_F0:RW:0:24:=0x0000ea
#define LP3_DENALI_CTL_DATA_14	0x0000091E // TINIT5_F0:RW:0:24:=0x00091e
#define LP3_DENALI_CTL_DATA_15	0x0000002F // TINIT_F1:RW:0:24:=0x00002f
#define LP3_DENALI_CTL_DATA_16	0x00016C90 // TINIT3_F1:RW:0:24:=0x016c90
#define LP3_DENALI_CTL_DATA_17	0x000001D3 // TINIT4_F1:RW:0:24:=0x0001d3
#define LP3_DENALI_CTL_DATA_18	0x0000123B // TINIT5_F1:RW:0:24:=0x00123b
#define LP3_DENALI_CTL_DATA_19	0x0000003F // TINIT_F2:RW:0:24:=0x00003f
#define LP3_DENALI_CTL_DATA_20	0x0001E5DB // TINIT3_F2:RW:0:24:=0x01e5db
#define LP3_DENALI_CTL_DATA_21	0x0000026E // TINIT4_F2:RW:0:24:=0x00026e
#define LP3_DENALI_CTL_DATA_22	0x0000184B // TINIT5_F2:RW:0:24:=0x00184b
#define LP3_DENALI_CTL_DATA_23	0x0000005E // TINIT_F3:RW:0:24:=0x00005e
#define LP3_DENALI_CTL_DATA_24	0x0002D976 // TINIT3_F3:RW:0:24:=0x02d976
#define LP3_DENALI_CTL_DATA_25	0x000003A6 // TINIT4_F3:RW:0:24:=0x0003a6
#define LP3_DENALI_CTL_DATA_26	0x0000247A // TINIT5_F3:RW:0:24:=0x00247a
#define LP3_DENALI_CTL_DATA_27	0x00000018 // TINIT_F4:RW:0:24:=0x000018
#define LP3_DENALI_CTL_DATA_28	0x0000B648 // TINIT3_F4:RW:0:24:=0x00b648
#define LP3_DENALI_CTL_DATA_29	0x000000EA // TINIT4_F4:RW:0:24:=0x0000ea
#define LP3_DENALI_CTL_DATA_30	0x0000091E // NO_AUTO_MRR_INIT:RW:24:1:=0x00 TINIT5_F4:RW:0:24:=0x00091e
#define LP3_DENALI_CTL_DATA_31	0x00000000 // NO_MRW_INIT:RW:24:1:=0x00 NO_MRW_BT_INIT:RW:16:1:=0x00 DFI_INV_DATA_CS:RW:8:1:=0x00 MRR_ERROR_STATUS:RD:0:2:=0x00
#define LP3_DENALI_CTL_DATA_32	0x00000101 // DFIBUS_BOOT_FREQ:RW:24:3:=0x00 DFIBUS_FREQ_INIT:RW:16:3:=0x00 PHY_INDEP_TRAIN_MODE:RW:8:1:=0x01 NO_PHY_IND_TRAIN_INIT:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_33	0x03020100 // DFIBUS_FREQ_F3:RW:24:5:=0x03 DFIBUS_FREQ_F2:RW:16:5:=0x02 DFIBUS_FREQ_F1:RW:8:5:=0x01 DFIBUS_FREQ_F0:RW:0:5:=0x00
#define LP3_DENALI_CTL_DATA_34	0x00000004 // DFIBUS_FREQ_F4:RW:0:5:=0x04
#define LP3_DENALI_CTL_DATA_35	0x0000002F // TRST_PWRON:RW:0:32:=0x0000002f
#define LP3_DENALI_CTL_DATA_36	0x00000075 // CKE_INACTIVE:RW:0:32:=0x00000075
#define LP3_DENALI_CTL_DATA_37	0x0410030C // WRLAT_F1:RW:24:7:=0x04 CASLAT_LIN_F1:RW:16:7:=0x10 WRLAT_F0:RW:8:7:=0x03 CASLAT_LIN_F0:RW:0:7:=0x0c
#define LP3_DENALI_CTL_DATA_38	0x081C0614 // WRLAT_F3:RW:24:7:=0x08 CASLAT_LIN_F3:RW:16:7:=0x1c WRLAT_F2:RW:8:7:=0x06 CASLAT_LIN_F2:RW:0:7:=0x14
#define LP3_DENALI_CTL_DATA_39	0x0404030C // TCCD:RW:24:5:=0x04 TBST_INT_INTERVAL:RW:16:3:=0x04 WRLAT_F4:RW:8:7:=0x03 CASLAT_LIN_F4:RW:0:7:=0x0c
#define LP3_DENALI_CTL_DATA_40	0x0A0F0300 // TRAS_MIN_F0:RW:24:8:=0x0a TRC_F0:RW:16:8:=0x0f TRRD_F0:RW:8:8:=0x03 TCCDMW:RW:0:6:=0x00
#define LP3_DENALI_CTL_DATA_41	0x010C0504 // CA_DEFAULT_VAL_F0:RW:24:1:=0x01 TFAW_F0:RW:16:8:=0x0c TRP_F0:RW:8:8:=0x05 TWTR_F0:RW:0:6:=0x04
#define LP3_DENALI_CTL_DATA_42	0x04141E05 // TWTR_F1:RW:24:6:=0x04 TRAS_MIN_F1:RW:16:8:=0x14 TRC_F1:RW:8:8:=0x1e TRRD_F1:RW:0:8:=0x05
#define LP3_DENALI_CTL_DATA_43	0x07011809 // TRRD_F2:RW:24:8:=0x07 CA_DEFAULT_VAL_F1:RW:16:1:=0x01 TFAW_F1:RW:8:8:=0x18 TRP_F1:RW:0:8:=0x09
#define LP3_DENALI_CTL_DATA_44	0x0C051B28 // TRP_F2:RW:24:8:=0x0c TWTR_F2:RW:16:6:=0x05 TRAS_MIN_F2:RW:8:8:=0x1b TRC_F2:RW:0:8:=0x28
#define LP3_DENALI_CTL_DATA_45	0x3B0A0120 // TRC_F3:RW:24:8:=0x3b TRRD_F3:RW:16:8:=0x0a CA_DEFAULT_VAL_F2:RW:8:1:=0x01 TFAW_F2:RW:0:8:=0x20
#define LP3_DENALI_CTL_DATA_46	0x2F110828 // TFAW_F3:RW:24:8:=0x2f TRP_F3:RW:16:8:=0x11 TWTR_F3:RW:8:6:=0x08 TRAS_MIN_F3:RW:0:8:=0x28
#define LP3_DENALI_CTL_DATA_47	0x0A0F0301 // TRAS_MIN_F4:RW:24:8:=0x0a TRC_F4:RW:16:8:=0x0f TRRD_F4:RW:8:8:=0x03 CA_DEFAULT_VAL_F3:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_48	0x010C0504 // CA_DEFAULT_VAL_F4:RW:24:1:=0x01 TFAW_F4:RW:16:8:=0x0c TRP_F4:RW:8:8:=0x05 TWTR_F4:RW:0:6:=0x04
#define LP3_DENALI_CTL_DATA_49	0x000A0A04 // TMOD_F0:RW:16:8:=0x0a TMRD_F0:RW:8:8:=0x0a TRTP_F0:RW:0:8:=0x04
#define LP3_DENALI_CTL_DATA_50	0x03003FCC // TCKE_F0:RW:24:4:=0x03 TRAS_MAX_F0:RW:0:17:=0x003fcc
#define LP3_DENALI_CTL_DATA_51	0x0A0A0404 // TMOD_F1:RW:24:8:=0x0a TMRD_F1:RW:16:8:=0x0a TRTP_F1:RW:8:8:=0x04 TCKESR_F0:RW:0:8:=0x04
#define LP3_DENALI_CTL_DATA_52	0x04007F98 // TCKE_F1:RW:24:4:=0x04 TRAS_MAX_F1:RW:0:17:=0x007f98
#define LP3_DENALI_CTL_DATA_53	0x0A0A0507 // TMOD_F2:RW:24:8:=0x0a TMRD_F2:RW:16:8:=0x0a TRTP_F2:RW:8:8:=0x05 TCKESR_F1:RW:0:8:=0x07
#define LP3_DENALI_CTL_DATA_54	0x0500AA0C // TCKE_F2:RW:24:4:=0x05 TRAS_MAX_F2:RW:0:17:=0x00aa0c
#define LP3_DENALI_CTL_DATA_55	0x0A0A080A // TMOD_F3:RW:24:8:=0x0a TMRD_F3:RW:16:8:=0x0a TRTP_F3:RW:8:8:=0x08 TCKESR_F2:RW:0:8:=0x0a
#define LP3_DENALI_CTL_DATA_56	0x0800FF4F // TCKE_F3:RW:24:4:=0x08 TRAS_MAX_F3:RW:0:17:=0x00ff4f
#define LP3_DENALI_CTL_DATA_57	0x0A0A040F // TMOD_F4:RW:24:8:=0x0a TMRD_F4:RW:16:8:=0x0a TRTP_F4:RW:8:8:=0x04 TCKESR_F3:RW:0:8:=0x0f
#define LP3_DENALI_CTL_DATA_58	0x03003FCC // TCKE_F4:RW:24:4:=0x03 TRAS_MAX_F4:RW:0:17:=0x003fcc
#define LP3_DENALI_CTL_DATA_59	0x02030004 // RESERVED:RW:24:3:=0x02 RESERVED:RW:16:3:=0x03 TPPD:RW_D:8:3:=0x00 TCKESR_F4:RW:0:8:=0x04
#define LP3_DENALI_CTL_DATA_60	0x09040500 // TRCD_F1:RW:24:8:=0x09 TWR_F0:RW:16:6:=0x04 TRCD_F0:RW:8:8:=0x05 WRITEINTERP:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_61	0x110A0C07 // TRCD_F3:RW:24:8:=0x11 TWR_F2:RW:16:6:=0x0a TRCD_F2:RW:8:8:=0x0c TWR_F1:RW:0:6:=0x07
#define LP3_DENALI_CTL_DATA_62	0x0404050F // TMRR:RW:24:4:=0x04 TWR_F4:RW:16:6:=0x04 TRCD_F4:RW:8:8:=0x05 TWR_F3:RW:0:6:=0x0f
#define LP3_DENALI_CTL_DATA_63	0x14000A0A // TCAMRD:RW:24:6:=0x14 TCAENT:RW:8:10:=0x000a TCACKEL:RW:0:5:=0x0a
#define LP3_DENALI_CTL_DATA_64	0x02010A0A // TMRZ_F1:RW:24:5:=0x02 TMRZ_F0:RW:16:5:=0x01 TCACKEH:RW:8:5:=0x0a TCAEXT:RW:0:5:=0x0a
#define LP3_DENALI_CTL_DATA_65	0x00010302 // AP:RW:24:1:=0x00 TMRZ_F4:RW:16:5:=0x01 TMRZ_F3:RW:8:5:=0x03 TMRZ_F2:RW:0:5:=0x02
#define LP3_DENALI_CTL_DATA_66	0x110B0101 // TDAL_F1:RW:24:8:=0x11 TDAL_F0:RW:16:8:=0x0b TRAS_LOCKOUT:RW:8:1:=0x01 CONCURRENTAP:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_67	0x030B2116 // BSTLEN:RW_D:24:5:=0x03 TDAL_F4:RW:16:8:=0x0b TDAL_F3:RW:8:8:=0x21 TDAL_F2:RW:0:8:=0x16
#define LP3_DENALI_CTL_DATA_68	0x140E0A05 // TRP_AB_F3:RW:24:8:=0x14 TRP_AB_F2:RW:16:8:=0x0e TRP_AB_F1:RW:8:8:=0x0a TRP_AB_F0:RW:0:8:=0x05
#define LP3_DENALI_CTL_DATA_69	0x01010005 // RESERVED:RW:24:1:=0x01 OPTIMAL_RMODW_EN:RW:16:1:=0x01 REG_DIMM_ENABLE:RW:8:1:=0x00 TRP_AB_F4:RW:0:8:=0x05
#define LP3_DENALI_CTL_DATA_70	0x01000000 // TREF_ENABLE:RW:24:1:=0x01 RESERVED:RW:16:1:=0x00 AREFRESH:WR:8:1:=0x00 NO_MEMORY_DM:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_71	0x00003103 // TRFC_F0:RW:8:10:=0x0031 RESERVED:RW:0:3:=0x03
#define LP3_DENALI_CTL_DATA_72	0x00620381 // TRFC_F1:RW:16:10:=0x0062 TREF_F0:RW:0:16:=0x0381
#define LP3_DENALI_CTL_DATA_73	0x00830702 // TRFC_F2:RW:16:10:=0x0083 TREF_F1:RW:0:16:=0x0702
#define LP3_DENALI_CTL_DATA_74	0x00C50956 // TRFC_F3:RW:16:10:=0x00c5 TREF_F2:RW:0:16:=0x0956
#define LP3_DENALI_CTL_DATA_75	0x00310E04 // TRFC_F4:RW:16:10:=0x0031 TREF_F3:RW:0:16:=0x0e04
#define LP3_DENALI_CTL_DATA_76	0x00000385 // TREF_F4:RW:0:16:=0x0385
#define LP3_DENALI_CTL_DATA_77	0x00040003 // TPDEX_F1:RW:16:16:=0x0004 TPDEX_F0:RW:0:16:=0x0003
#define LP3_DENALI_CTL_DATA_78	0x00080005 // TPDEX_F3:RW:16:16:=0x0008 TPDEX_F2:RW:0:16:=0x0005
#define LP3_DENALI_CTL_DATA_79	0x00000003 // SHUTDOWN_STATUS:RD:24:6:=0x00 SHUTDOWN_MEM_GATE:RW:16:1:=0x00 TPDEX_F4:RW:0:16:=0x0003
#define LP3_DENALI_CTL_DATA_80	0x110C0905 // TMRRI_F3:RW:24:8:=0x11 TMRRI_F2:RW:16:8:=0x0c TMRRI_F1:RW:8:8:=0x09 TMRRI_F0:RW:0:8:=0x05
#define LP3_DENALI_CTL_DATA_81	0x00000005 // TCKEHCS_F0:RW:24:4:=0x00 TCKELCS_F0:RW:16:4:=0x00 TCSCKE_F0:RW:8:4:=0x00 TMRRI_F4:RW:0:8:=0x05
#define LP3_DENALI_CTL_DATA_82	0x00000000 // TCKELCS_F1:RW:24:4:=0x00 TCSCKE_F1:RW:16:4:=0x00 TZQCKE_F0:RW:8:4:=0x00 TMRWCKEL_F0:RW:0:5:=0x00
#define LP3_DENALI_CTL_DATA_83	0x00000000 // TCSCKE_F2:RW:24:4:=0x00 TZQCKE_F1:RW:16:4:=0x00 TMRWCKEL_F1:RW:8:5:=0x00 TCKEHCS_F1:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_84	0x00000000 // TZQCKE_F2:RW:24:4:=0x00 TMRWCKEL_F2:RW:16:5:=0x00 TCKEHCS_F2:RW:8:4:=0x00 TCKELCS_F2:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_85	0x00000000 // TMRWCKEL_F3:RW:24:5:=0x00 TCKEHCS_F3:RW:16:4:=0x00 TCKELCS_F3:RW:8:4:=0x00 TCSCKE_F3:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_86	0x00000000 // TCKEHCS_F4:RW:24:4:=0x00 TCKELCS_F4:RW:16:4:=0x00 TCSCKE_F4:RW:8:4:=0x00 TZQCKE_F3:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_87	0x00340000 // TXSR_F0:RW:16:16:=0x0034 TZQCKE_F4:RW:8:4:=0x00 TMRWCKEL_F4:RW:0:5:=0x00
#define LP3_DENALI_CTL_DATA_88	0x00670034 // TXSR_F1:RW:16:16:=0x0067 TXSNR_F0:RW:0:16:=0x0034
#define LP3_DENALI_CTL_DATA_89	0x00890067 // TXSR_F2:RW:16:16:=0x0089 TXSNR_F1:RW:0:16:=0x0067
#define LP3_DENALI_CTL_DATA_90	0x00CE0089 // TXSR_F3:RW:16:16:=0x00ce TXSNR_F2:RW:0:16:=0x0089
#define LP3_DENALI_CTL_DATA_91	0x003400CE // TXSR_F4:RW:16:16:=0x0034 TXSNR_F3:RW:0:16:=0x00ce
#define LP3_DENALI_CTL_DATA_92	0x00000034 // TCKEHCMD_F0:RW:24:4:=0x00 TCKELCMD_F0:RW:16:4:=0x00 TXSNR_F4:RW:0:16:=0x0034
#define LP3_DENALI_CTL_DATA_93	0x00000000 // TCKELPD_F0:RW:24:4:=0x00 TESCKE_F0:RW:16:3:=0x00 TSR_F0:RW:8:8:=0x00 TCKCKEL_F0:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_94	0x00000000 // TCKEHCMD_F1:RW:24:4:=0x00 TCKELCMD_F1:RW:16:4:=0x00 TCMDCKE_F0:RW:8:4:=0x00 TCSCKEH_F0:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_95	0x00000000 // TCKELPD_F1:RW:24:4:=0x00 TESCKE_F1:RW:16:3:=0x00 TSR_F1:RW:8:8:=0x00 TCKCKEL_F1:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_96	0x00000000 // TCKEHCMD_F2:RW:24:4:=0x00 TCKELCMD_F2:RW:16:4:=0x00 TCMDCKE_F1:RW:8:4:=0x00 TCSCKEH_F1:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_97	0x00000000 // TCKELPD_F2:RW:24:4:=0x00 TESCKE_F2:RW:16:3:=0x00 TSR_F2:RW:8:8:=0x00 TCKCKEL_F2:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_98	0x00000000 // TCKEHCMD_F3:RW:24:4:=0x00 TCKELCMD_F3:RW:16:4:=0x00 TCMDCKE_F2:RW:8:4:=0x00 TCSCKEH_F2:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_99	0x00000000 // TCKELPD_F3:RW:24:4:=0x00 TESCKE_F3:RW:16:3:=0x00 TSR_F3:RW:8:8:=0x00 TCKCKEL_F3:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_100	0x00000000 // TCKEHCMD_F4:RW:24:4:=0x00 TCKELCMD_F4:RW:16:4:=0x00 TCMDCKE_F3:RW:8:4:=0x00 TCSCKEH_F3:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_101	0x00000000 // TCKELPD_F4:RW:24:4:=0x00 TESCKE_F4:RW:16:3:=0x00 TSR_F4:RW:8:8:=0x00 TCKCKEL_F4:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_102	0x00000000 // SREFRESH_EXIT_NO_REFRESH:RW:24:1:=0x00 PWRUP_SREFRESH_EXIT:RW:16:1:=0x00 TCMDCKE_F4:RW:8:4:=0x00 TCSCKEH_F4:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_103	0x00000301 // RESERVED:WR:16:9:=0x0000 CKE_DELAY:RW:8:3:=0x03 ENABLE_QUICK_SREFRESH:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_104	0x00000100 // DFS_WRLVL_EN:RW:24:1:=0x00 DFS_CALVL_EN:RW:16:1:=0x00 DFS_ZQ_EN:RW:8:1:=0x01 DFS_STATUS:RD:0:2:=0x00
#define LP3_DENALI_CTL_DATA_105	0x00000000 // DFS_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 DFS_RDLVL_GATE_EN:RW:8:1:=0x00 DFS_RDLVL_EN:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_106	0x00000000 // DFS_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 DFS_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_107	0x00000000 // DFS_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 DFS_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_108	0x01000000 // RESERVED:RW:24:3:=0x01 ZQ_CALINIT_CS_CL_STATUS:RD:16:2:=0x00 ZQ_CALLATCH_STATUS:RD:8:2:=0x00 ZQ_CALSTART_STATUS:RD:0:2:=0x00
#define LP3_DENALI_CTL_DATA_109	0x80104002 // RESERVED:RW:24:8:=0x80 RESERVED:RW:16:8:=0x10 RESERVED:RW:8:8:=0x40 RESERVED:RW:0:3:=0x02
#define LP3_DENALI_CTL_DATA_110	0x00040003 // UPD_CTRLUPD_HIGH_THRESHOLD_F0:RW:16:16:=0x0004 UPD_CTRLUPD_NORM_THRESHOLD_F0:RW:0:16:=0x0003
#define LP3_DENALI_CTL_DATA_111	0x00040005 // UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0004 UPD_CTRLUPD_TIMEOUT_F0:RW:0:16:=0x0005
#define LP3_DENALI_CTL_DATA_112	0x00030000 // UPD_CTRLUPD_NORM_THRESHOLD_F1:RW:16:16:=0x0003 UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_113	0x00050004 // UPD_CTRLUPD_TIMEOUT_F1:RW:16:16:=0x0005 UPD_CTRLUPD_HIGH_THRESHOLD_F1:RW:0:16:=0x0004
#define LP3_DENALI_CTL_DATA_114	0x00000004 // UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0004
#define LP3_DENALI_CTL_DATA_115	0x00040003 // UPD_CTRLUPD_HIGH_THRESHOLD_F2:RW:16:16:=0x0004 UPD_CTRLUPD_NORM_THRESHOLD_F2:RW:0:16:=0x0003
#define LP3_DENALI_CTL_DATA_116	0x00040005 // UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0004 UPD_CTRLUPD_TIMEOUT_F2:RW:0:16:=0x0005
#define LP3_DENALI_CTL_DATA_117	0x00030000 // UPD_CTRLUPD_NORM_THRESHOLD_F3:RW:16:16:=0x0003 UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_118	0x00050004 // UPD_CTRLUPD_TIMEOUT_F3:RW:16:16:=0x0005 UPD_CTRLUPD_HIGH_THRESHOLD_F3:RW:0:16:=0x0004
#define LP3_DENALI_CTL_DATA_119	0x00000004 // UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0004
#define LP3_DENALI_CTL_DATA_120	0x00040003 // UPD_CTRLUPD_HIGH_THRESHOLD_F4:RW:16:16:=0x0004 UPD_CTRLUPD_NORM_THRESHOLD_F4:RW:0:16:=0x0003
#define LP3_DENALI_CTL_DATA_121	0x00040005 // UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0004 UPD_CTRLUPD_TIMEOUT_F4:RW:0:16:=0x0005
#define LP3_DENALI_CTL_DATA_122	0x0E140000 // TDFI_PHYMSTR_MAX_F0:RW:16:16:=0x0e14 UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_123	0x0000070A // PHYMSTR_DFI_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 TDFI_PHYMSTR_RESP_F0:RW:0:16:=0x070a
#define LP3_DENALI_CTL_DATA_124	0x0E261C4C // TDFI_PHYMSTR_RESP_F1:RW:16:16:=0x0e26 TDFI_PHYMSTR_MAX_F1:RW:0:16:=0x1c4c
#define LP3_DENALI_CTL_DATA_125	0x25C40000 // TDFI_PHYMSTR_MAX_F2:RW:16:16:=0x25c4 PHYMSTR_DFI_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_126	0x000012E2 // PHYMSTR_DFI_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 TDFI_PHYMSTR_RESP_F2:RW:0:16:=0x12e2
#define LP3_DENALI_CTL_DATA_127	0x1C6238C4 // TDFI_PHYMSTR_RESP_F3:RW:16:16:=0x1c62 TDFI_PHYMSTR_MAX_F3:RW:0:16:=0x38c4
#define LP3_DENALI_CTL_DATA_128	0x0E140000 // TDFI_PHYMSTR_MAX_F4:RW:16:16:=0x0e14 PHYMSTR_DFI_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_129	0x0000070A // PHYMSTR_DFI_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 TDFI_PHYMSTR_RESP_F4:RW:0:16:=0x070a
#define LP3_DENALI_CTL_DATA_130	0x00000000 // MRR_TEMPCHK_NORM_THRESHOLD_F0:RW:16:16:=0x0000 PHYMSTR_ERROR_STATUS:RD:8:2:=0x00 PHYMSTR_NO_AREF:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_131	0x00000000 // MRR_TEMPCHK_TIMEOUT_F0:RW:16:16:=0x0000 MRR_TEMPCHK_HIGH_THRESHOLD_F0:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_132	0x00000000 // MRR_TEMPCHK_HIGH_THRESHOLD_F1:RW:16:16:=0x0000 MRR_TEMPCHK_NORM_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_133	0x00000000 // MRR_TEMPCHK_NORM_THRESHOLD_F2:RW:16:16:=0x0000 MRR_TEMPCHK_TIMEOUT_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_134	0x00000000 // MRR_TEMPCHK_TIMEOUT_F2:RW:16:16:=0x0000 MRR_TEMPCHK_HIGH_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_135	0x00000000 // MRR_TEMPCHK_HIGH_THRESHOLD_F3:RW:16:16:=0x0000 MRR_TEMPCHK_NORM_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_136	0x00000000 // MRR_TEMPCHK_NORM_THRESHOLD_F4:RW:16:16:=0x0000 MRR_TEMPCHK_TIMEOUT_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_137	0x00000000 // MRR_TEMPCHK_TIMEOUT_F4:RW:16:16:=0x0000 MRR_TEMPCHK_HIGH_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_138	0x02020200 // CKSRE_F1:RW:24:8:=0x02 CKSRX_F0:RW:16:8:=0x02 CKSRE_F0:RW:8:8:=0x02 LOWPOWER_REFRESH_ENABLE:RW:0:2:=0x00
#define LP3_DENALI_CTL_DATA_139	0x02020202 // CKSRE_F3:RW:24:8:=0x02 CKSRX_F2:RW:16:8:=0x02 CKSRE_F2:RW:8:8:=0x02 CKSRX_F1:RW:0:8:=0x02
#define LP3_DENALI_CTL_DATA_140	0x00020202 // CKSRX_F4:RW:16:8:=0x02 CKSRE_F4:RW:8:8:=0x02 CKSRX_F3:RW:0:8:=0x02
#define LP3_DENALI_CTL_DATA_141	0x02000000 // LPI_SR_WAKEUP_F0:RW:24:4:=0x02 LPI_PD_WAKEUP_F0:RW:16:4:=0x00 LP_CMD:WR:0:9:=0x0000
#define LP3_DENALI_CTL_DATA_142	0x07030203 // LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F0:RW:24:4:=0x07 LPI_SRPD_DEEP_WAKEUP_F0:RW:16:4:=0x03 LPI_SRPD_LITE_WAKEUP_F0:RW:8:4:=0x02 LPI_SR_MCCLK_GATE_WAKEUP_F0:RW:0:4:=0x03
#define LP3_DENALI_CTL_DATA_143	0x0200040F // LPI_SR_WAKEUP_F1:RW:24:4:=0x02 LPI_PD_WAKEUP_F1:RW:16:4:=0x00 LPI_TIMER_WAKEUP_F0:RW:8:4:=0x04 LPI_DPD_WAKEUP_F0:RW:0:4:=0x0f
#define LP3_DENALI_CTL_DATA_144	0x07030203 // LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F1:RW:24:4:=0x07 LPI_SRPD_DEEP_WAKEUP_F1:RW:16:4:=0x03 LPI_SRPD_LITE_WAKEUP_F1:RW:8:4:=0x02 LPI_SR_MCCLK_GATE_WAKEUP_F1:RW:0:4:=0x03
#define LP3_DENALI_CTL_DATA_145	0x0200040F // LPI_SR_WAKEUP_F2:RW:24:4:=0x02 LPI_PD_WAKEUP_F2:RW:16:4:=0x00 LPI_TIMER_WAKEUP_F1:RW:8:4:=0x04 LPI_DPD_WAKEUP_F1:RW:0:4:=0x0f
#define LP3_DENALI_CTL_DATA_146	0x07030203 // LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F2:RW:24:4:=0x07 LPI_SRPD_DEEP_WAKEUP_F2:RW:16:4:=0x03 LPI_SRPD_LITE_WAKEUP_F2:RW:8:4:=0x02 LPI_SR_MCCLK_GATE_WAKEUP_F2:RW:0:4:=0x03
#define LP3_DENALI_CTL_DATA_147	0x0200040F // LPI_SR_WAKEUP_F3:RW:24:4:=0x02 LPI_PD_WAKEUP_F3:RW:16:4:=0x00 LPI_TIMER_WAKEUP_F2:RW:8:4:=0x04 LPI_DPD_WAKEUP_F2:RW:0:4:=0x0f
#define LP3_DENALI_CTL_DATA_148	0x07030203 // LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F3:RW:24:4:=0x07 LPI_SRPD_DEEP_WAKEUP_F3:RW:16:4:=0x03 LPI_SRPD_LITE_WAKEUP_F3:RW:8:4:=0x02 LPI_SR_MCCLK_GATE_WAKEUP_F3:RW:0:4:=0x03
#define LP3_DENALI_CTL_DATA_149	0x0200040F // LPI_SR_WAKEUP_F4:RW:24:4:=0x02 LPI_PD_WAKEUP_F4:RW:16:4:=0x00 LPI_TIMER_WAKEUP_F3:RW:8:4:=0x04 LPI_DPD_WAKEUP_F3:RW:0:4:=0x0f
#define LP3_DENALI_CTL_DATA_150	0x07030203 // LPI_SRPD_DEEP_MCCLK_GATE_WAKEUP_F4:RW:24:4:=0x07 LPI_SRPD_DEEP_WAKEUP_F4:RW:16:4:=0x03 LPI_SRPD_LITE_WAKEUP_F4:RW:8:4:=0x02 LPI_SR_MCCLK_GATE_WAKEUP_F4:RW:0:4:=0x03
#define LP3_DENALI_CTL_DATA_151	0x000F040F // LPI_WAKEUP_EN:RW:16:5:=0x0f LPI_TIMER_WAKEUP_F4:RW:8:4:=0x04 LPI_DPD_WAKEUP_F4:RW:0:4:=0x0f
#define LP3_DENALI_CTL_DATA_152	0x00040003 // LPI_WAKEUP_TIMEOUT:RW:16:12:=0x0004 LPI_TIMER_COUNT:RW:0:12:=0x0003
#define LP3_DENALI_CTL_DATA_153	0x00000007 // LP_AUTO_ENTRY_EN:RW:24:4:=0x00 LP_STATE_CS1:RD:16:6:=0x00 LP_STATE_CS0:RD:8:6:=0x00 TDFI_LP_RESP:RW:0:3:=0x07
#define LP3_DENALI_CTL_DATA_154	0x00000000 // LP_AUTO_PD_IDLE:RW:16:12:=0x0000 LP_AUTO_MEM_GATE_EN:RW:8:3:=0x00 LP_AUTO_EXIT_EN:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_155	0x00000000 // LP_AUTO_SR_MC_GATE_IDLE:RW:24:8:=0x00 LP_AUTO_SR_IDLE:RW:16:8:=0x00 LP_AUTO_SRPD_LITE_IDLE:RW:0:12:=0x0000
#define LP3_DENALI_CTL_DATA_156	0x00000000 // HW_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 HW_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_157	0x00000000 // HW_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 HW_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_158	0x00000000 // LPC_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 HW_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_159	0x00000000 // LPC_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 LPC_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_160	0x00000000 // LPC_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 LPC_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_161	0x00000000 // RESERVED:RW:24:1:=0x00 LPC_SR_PHYMSTR_EN:RW:16:1:=0x00 LPC_SR_PHYUPD_EN:RW:8:1:=0x00 LPC_SR_CTRLUPD_EN:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_162	0x04040100 // PCPCS_PD_EXIT_DEPTH:RW:24:5:=0x04 PCPCS_PD_ENTER_DEPTH:RW:16:5:=0x04 PCPCS_PD_EN:RW:8:1:=0x01 LPC_SR_ZQ_EN:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_163	0x00030000 // LP_CS:RW:24:2:=0x00 PCPCS_CS_MAP:RW:16:2:=0x03 PCPCS_PD_MASK:RW:8:2:=0x00 PCPCS_PD_ENTER_TIMER:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_164	0x00000000 // CS1_IDLE:RD:8:1:=0x00 CS0_IDLE:RD:0:1:=0x00
#define LP3_DENALI_CTL_DATA_165	0x0001C7B3 // TDPD_F0:RW:0:24:=0x01c7b3
#define LP3_DENALI_CTL_DATA_166	0x00038F66 // TDPD_F1:RW:0:24:=0x038f66
#define LP3_DENALI_CTL_DATA_167	0x0004BEA2 // TDPD_F2:RW:0:24:=0x04bea2
#define LP3_DENALI_CTL_DATA_168	0x00071FA6 // TDPD_F3:RW:0:24:=0x071fa6
#define LP3_DENALI_CTL_DATA_169	0x0001C7B3 // TDPD_CNT_DONE_STATUS:RD:24:2:=0x00 TDPD_F4:RW:0:24:=0x01c7b3
#define LP3_DENALI_CTL_DATA_170	0xC0010003 // TDFI_INIT_START_F0:RW_D:24:8:=0xc0 DFS_ENABLE:RW:16:1:=0x01 RESERVED:RW:8:8:=0x00 PWRUP_SREFRESH_EXIT_CS:RW:0:2:=0x03
#define LP3_DENALI_CTL_DATA_171	0x00C01000 // TDFI_INIT_START_F1:RW_D:16:8:=0xc0 TDFI_INIT_COMPLETE_F0:RW_D:0:16:=0x1000
#define LP3_DENALI_CTL_DATA_172	0x00C01000 // TDFI_INIT_START_F2:RW_D:16:8:=0xc0 TDFI_INIT_COMPLETE_F1:RW_D:0:16:=0x1000
#define LP3_DENALI_CTL_DATA_173	0x00C01000 // TDFI_INIT_START_F3:RW_D:16:8:=0xc0 TDFI_INIT_COMPLETE_F2:RW_D:0:16:=0x1000
#define LP3_DENALI_CTL_DATA_174	0x00C01000 // TDFI_INIT_START_F4:RW_D:16:8:=0xc0 TDFI_INIT_COMPLETE_F3:RW_D:0:16:=0x1000
#define LP3_DENALI_CTL_DATA_175	0x01001000 // DFS_PHY_REG_WRITE_EN:RW:24:1:=0x01 CURRENT_REG_COPY:RD:16:3:=0x00 TDFI_INIT_COMPLETE_F4:RW_D:0:16:=0x1000
#define LP3_DENALI_CTL_DATA_176	0x00000C00 // DFS_PHY_REG_WRITE_ADDR:RW:0:32:=0x00000c00
#define LP3_DENALI_CTL_DATA_177	0x00000000 // DFS_PHY_REG_WRITE_DATA_F0:RW:0:32:=0x00000000
#define LP3_DENALI_CTL_DATA_178	0x00000001 // DFS_PHY_REG_WRITE_DATA_F1:RW:0:32:=0x00000001
#define LP3_DENALI_CTL_DATA_179	0x00000002 // DFS_PHY_REG_WRITE_DATA_F2:RW:0:32:=0x00000002
#define LP3_DENALI_CTL_DATA_180	0x00000003 // DFS_PHY_REG_WRITE_DATA_F3:RW:0:32:=0x00000003
#define LP3_DENALI_CTL_DATA_181	0x00000004 // DFS_PHY_REG_WRITE_DATA_F4:RW:0:32:=0x00000004
#define LP3_DENALI_CTL_DATA_182	0x0000000E // DFS_PHY_REG_WRITE_MASK:RW:0:4:=0x0e
#define LP3_DENALI_CTL_DATA_183	0x00000000 // WRITE_MODEREG:RW+:0:27:=0x00000000
#define LP3_DENALI_CTL_DATA_184	0x00000000 // READ_MODEREG:RW+:8:17:=0x000000 MRW_STATUS:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_185	0x00000000 // PERIPHERAL_MRR_DATA:RD:0:40:=0x00000000
#define LP3_DENALI_CTL_DATA_186	0x00000000 // AUTO_TEMPCHK_VAL_0:RD:8:16:=0x0000 PERIPHERAL_MRR_DATA:RD:0:40:=0x00
#define LP3_DENALI_CTL_DATA_187	0x00000000 // DISABLE_UPDATE_TVRCG:RW:16:1:=0x00 AUTO_TEMPCHK_VAL_1:RD:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_188	0x002F0000 // TVRCG_ENABLE_F0:RW:16:10:=0x002f MRW_DFS_UPDATE_FRC:RW:0:3:=0x00
#define LP3_DENALI_CTL_DATA_189	0x003B0018 // TFC_F0:RW:16:10:=0x003b TVRCG_DISABLE_F0:RW:0:10:=0x0018
#define LP3_DENALI_CTL_DATA_190	0x003B0000 // TVREF_LONG_F0:RW:16:16:=0x003b TCKFSPX_F0:RW:8:5:=0x00 TCKFSPE_F0:RW:0:5:=0x00
#define LP3_DENALI_CTL_DATA_191	0x002F005E // TVRCG_DISABLE_F1:RW:16:10:=0x002f TVRCG_ENABLE_F1:RW:0:10:=0x005e
#define LP3_DENALI_CTL_DATA_192	0x00000075 // TCKFSPX_F1:RW:24:5:=0x00 TCKFSPE_F1:RW:16:5:=0x00 TFC_F1:RW:0:10:=0x0075
#define LP3_DENALI_CTL_DATA_193	0x007D0075 // TVRCG_ENABLE_F2:RW:16:10:=0x007d TVREF_LONG_F1:RW:0:16:=0x0075
#define LP3_DENALI_CTL_DATA_194	0x009C003F // TFC_F2:RW:16:10:=0x009c TVRCG_DISABLE_F2:RW:0:10:=0x003f
#define LP3_DENALI_CTL_DATA_195	0x009C0000 // TVREF_LONG_F2:RW:16:16:=0x009c TCKFSPX_F2:RW:8:5:=0x00 TCKFSPE_F2:RW:0:5:=0x00
#define LP3_DENALI_CTL_DATA_196	0x005E00BB // TVRCG_DISABLE_F3:RW:16:10:=0x005e TVRCG_ENABLE_F3:RW:0:10:=0x00bb
#define LP3_DENALI_CTL_DATA_197	0x000000EA // TCKFSPX_F3:RW:24:5:=0x00 TCKFSPE_F3:RW:16:5:=0x00 TFC_F3:RW:0:10:=0x00ea
#define LP3_DENALI_CTL_DATA_198	0x002F00EA // TVRCG_ENABLE_F4:RW:16:10:=0x002f TVREF_LONG_F3:RW:0:16:=0x00ea
#define LP3_DENALI_CTL_DATA_199	0x003B0018 // TFC_F4:RW:16:10:=0x003b TVRCG_DISABLE_F4:RW:0:10:=0x0018
#define LP3_DENALI_CTL_DATA_200	0x003B0000 // TVREF_LONG_F4:RW:16:16:=0x003b TCKFSPX_F4:RW:8:5:=0x00 TCKFSPE_F4:RW:0:5:=0x00
#define LP3_DENALI_CTL_DATA_201	0x00000000 // MRR_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 MRR_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_202	0x00000000 // MRR_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 MRR_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_203	0x00000000 // MRW_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 MRR_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_204	0x00000000 // MRW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 MRW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_205	0x00000000 // MRW_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 MRW_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_206	0x06C30483 // MR2_DATA_F1_0:RW:24:8:=0x06 MR1_DATA_F1_0:RW:16:8:=0xc3 MR2_DATA_F0_0:RW:8:8:=0x04 MR1_DATA_F0_0:RW:0:8:=0x83
#define LP3_DENALI_CTL_DATA_207	0x1CC31803 // MR2_DATA_F3_0:RW:24:8:=0x1c MR1_DATA_F3_0:RW:16:8:=0xc3 MR2_DATA_F2_0:RW:8:8:=0x18 MR1_DATA_F2_0:RW:0:8:=0x03
#define LP3_DENALI_CTL_DATA_208	0x01000483 // MR3_DATA_F0_0:RW:24:8:=0x01 MRSINGLE_DATA_0:RW:16:8:=0x00 MR2_DATA_F4_0:RW:8:8:=0x04 MR1_DATA_F4_0:RW:0:8:=0x83
#define LP3_DENALI_CTL_DATA_209	0x01010101 // MR3_DATA_F4_0:RW:24:8:=0x01 MR3_DATA_F3_0:RW:16:8:=0x01 MR3_DATA_F2_0:RW:8:8:=0x01 MR3_DATA_F1_0:RW:0:8:=0x01
#define LP3_DENALI_CTL_DATA_210	0x07070700 // MR11_DATA_F2_0:RW:24:8:=0x07 MR11_DATA_F1_0:RW:16:8:=0x07 MR11_DATA_F0_0:RW:8:8:=0x07 MR8_DATA_0:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_211	0x00000707 // MR12_DATA_F1_0:RW:24:8:=0x00 MR12_DATA_F0_0:RW:16:8:=0x00 MR11_DATA_F4_0:RW:8:8:=0x07 MR11_DATA_F3_0:RW:0:8:=0x07
#define LP3_DENALI_CTL_DATA_212	0x00000000 // MR13_DATA_0:RW:24:8:=0x00 MR12_DATA_F4_0:RW:16:8:=0x00 MR12_DATA_F3_0:RW:8:8:=0x00 MR12_DATA_F2_0:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_213	0x00000000 // MR14_DATA_F3_0:RW:24:8:=0x00 MR14_DATA_F2_0:RW:16:8:=0x00 MR14_DATA_F1_0:RW:8:8:=0x00 MR14_DATA_F0_0:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_214	0x00000000 // MR_FSP_DATA_VALID_F2_0:RW:24:1:=0x00 MR_FSP_DATA_VALID_F1_0:RW:16:1:=0x00 MR_FSP_DATA_VALID_F0_0:RW:8:1:=0x00 MR14_DATA_F4_0:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_215	0x00000000 // MR17_DATA_0:RW:24:8:=0x00 MR16_DATA_0:RW:16:8:=0x00 MR_FSP_DATA_VALID_F4_0:RW:8:1:=0x00 MR_FSP_DATA_VALID_F3_0:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_216	0x00000000 // MR22_DATA_F2_0:RW:24:8:=0x00 MR22_DATA_F1_0:RW:16:8:=0x00 MR22_DATA_F0_0:RW:8:8:=0x00 MR20_DATA_0:RD:0:8:=0x00
#define LP3_DENALI_CTL_DATA_217	0x04830000 // MR2_DATA_F0_1:RW:24:8:=0x04 MR1_DATA_F0_1:RW:16:8:=0x83 MR22_DATA_F4_0:RW:8:8:=0x00 MR22_DATA_F3_0:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_218	0x180306C3 // MR2_DATA_F2_1:RW:24:8:=0x18 MR1_DATA_F2_1:RW:16:8:=0x03 MR2_DATA_F1_1:RW:8:8:=0x06 MR1_DATA_F1_1:RW:0:8:=0xc3
#define LP3_DENALI_CTL_DATA_219	0x04831CC3 // MR2_DATA_F4_1:RW:24:8:=0x04 MR1_DATA_F4_1:RW:16:8:=0x83 MR2_DATA_F3_1:RW:8:8:=0x1c MR1_DATA_F3_1:RW:0:8:=0xc3
#define LP3_DENALI_CTL_DATA_220	0x01010100 // MR3_DATA_F2_1:RW:24:8:=0x01 MR3_DATA_F1_1:RW:16:8:=0x01 MR3_DATA_F0_1:RW:8:8:=0x01 MRSINGLE_DATA_1:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_221	0x07000101 // MR11_DATA_F0_1:RW:24:8:=0x07 MR8_DATA_1:RD:16:8:=0x00 MR3_DATA_F4_1:RW:8:8:=0x01 MR3_DATA_F3_1:RW:0:8:=0x01
#define LP3_DENALI_CTL_DATA_222	0x07070707 // MR11_DATA_F4_1:RW:24:8:=0x07 MR11_DATA_F3_1:RW:16:8:=0x07 MR11_DATA_F2_1:RW:8:8:=0x07 MR11_DATA_F1_1:RW:0:8:=0x07
#define LP3_DENALI_CTL_DATA_223	0x00000000 // MR12_DATA_F3_1:RW:24:8:=0x00 MR12_DATA_F2_1:RW:16:8:=0x00 MR12_DATA_F1_1:RW:8:8:=0x00 MR12_DATA_F0_1:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_224	0x00000000 // MR14_DATA_F1_1:RW:24:8:=0x00 MR14_DATA_F0_1:RW:16:8:=0x00 MR13_DATA_1:RW:8:8:=0x00 MR12_DATA_F4_1:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_225	0x00000000 // MR_FSP_DATA_VALID_F0_1:RW:24:1:=0x00 MR14_DATA_F4_1:RW:16:8:=0x00 MR14_DATA_F3_1:RW:8:8:=0x00 MR14_DATA_F2_1:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_226	0x00000000 // MR_FSP_DATA_VALID_F4_1:RW:24:1:=0x00 MR_FSP_DATA_VALID_F3_1:RW:16:1:=0x00 MR_FSP_DATA_VALID_F2_1:RW:8:1:=0x00 MR_FSP_DATA_VALID_F1_1:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_227	0x00000000 // MR22_DATA_F0_1:RW:24:8:=0x00 MR20_DATA_1:RD:16:8:=0x00 MR17_DATA_1:RW:8:8:=0x00 MR16_DATA_1:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_228	0x00000000 // MR22_DATA_F4_1:RW:24:8:=0x00 MR22_DATA_F3_1:RW:16:8:=0x00 MR22_DATA_F2_1:RW:8:8:=0x00 MR22_DATA_F1_1:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_229	0x01000000 // FSP_PHY_UPDATE_MRW:RW:24:1:=0x01 RESERVED:RD:16:1:=0x00 RESERVED:RD:8:1:=0x00 RL3_SUPPORT_EN:RD:0:2:=0x00
#define LP3_DENALI_CTL_DATA_230	0x00000000 // FSP_WR_CURRENT:RW+:24:1:=0x00 FSP_OP_CURRENT:RW+:16:1:=0x00 FSP_STATUS:RW:8:1:=0x00 DFS_ALWAYS_WRITE_FSP:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_231	0x00000000 // FSP1_FRC:RW+:24:3:=0x00 FSP0_FRC:RW+:16:3:=0x00 FSP1_FRC_VALID:RW+:8:1:=0x00 FSP0_FRC_VALID:RW+:0:1:=0x00
#define LP3_DENALI_CTL_DATA_232	0x01000000 // BIST_DATA_CHECK:RW:24:1:=0x01 ADDR_SPACE:RW:16:6:=0x00 BIST_RESULT:RD:8:2:=0x00 BIST_GO:WR:0:1:=0x00
#define LP3_DENALI_CTL_DATA_233	0x00000001 // BIST_ADDR_CHECK:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_234	0x00000000 // BIST_START_ADDRESS:RW:0:34:=0x00000000
#define LP3_DENALI_CTL_DATA_235	0x00000000 // BIST_START_ADDRESS:RW:0:34:=0x00
#define LP3_DENALI_CTL_DATA_236	0x00000000 // BIST_DATA_MASK:RW:0:64:=0x00000000
#define LP3_DENALI_CTL_DATA_237	0x00000000 // BIST_DATA_MASK:RW:0:64:=0x00000000
#define LP3_DENALI_CTL_DATA_238	0x18151100 // AREF_MAX_DEFICIT:RW:24:5:=0x18 AREF_HIGH_THRESHOLD:RW:16:5:=0x15 AREF_NORM_THRESHOLD:RW:8:5:=0x11 LONG_COUNT_MASK:RW:0:5:=0x00
#define LP3_DENALI_CTL_DATA_239	0x0000000C // ZQ_CALSTART_NORM_THRESHOLD_F0:RW:8:16:=0x0000 AREF_MAX_CREDIT:RW:0:5:=0x0c
#define LP3_DENALI_CTL_DATA_240	0x00000000 // ZQ_CALLATCH_HIGH_THRESHOLD_F0:RW:16:16:=0x0000 ZQ_CALSTART_HIGH_THRESHOLD_F0:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_241	0x00000000 // ZQ_CS_HIGH_THRESHOLD_F0:RW:16:16:=0x0000 ZQ_CS_NORM_THRESHOLD_F0:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_242	0x00000000 // ZQ_CALLATCH_TIMEOUT_F0:RW:16:16:=0x0000 ZQ_CALSTART_TIMEOUT_F0:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_243	0x00000000 // ZQ_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 ZQ_CS_TIMEOUT_F0:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_244	0x00000000 // ZQ_CALSTART_HIGH_THRESHOLD_F1:RW:16:16:=0x0000 ZQ_CALSTART_NORM_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_245	0x00000000 // ZQ_CS_NORM_THRESHOLD_F1:RW:16:16:=0x0000 ZQ_CALLATCH_HIGH_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_246	0x00000000 // ZQ_CALSTART_TIMEOUT_F1:RW:16:16:=0x0000 ZQ_CS_HIGH_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_247	0x00000000 // ZQ_CS_TIMEOUT_F1:RW:16:16:=0x0000 ZQ_CALLATCH_TIMEOUT_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_248	0x00000000 // ZQ_CALSTART_NORM_THRESHOLD_F2:RW:16:16:=0x0000 ZQ_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_249	0x00000000 // ZQ_CALLATCH_HIGH_THRESHOLD_F2:RW:16:16:=0x0000 ZQ_CALSTART_HIGH_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_250	0x00000000 // ZQ_CS_HIGH_THRESHOLD_F2:RW:16:16:=0x0000 ZQ_CS_NORM_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_251	0x00000000 // ZQ_CALLATCH_TIMEOUT_F2:RW:16:16:=0x0000 ZQ_CALSTART_TIMEOUT_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_252	0x00000000 // ZQ_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 ZQ_CS_TIMEOUT_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_253	0x00000000 // ZQ_CALSTART_HIGH_THRESHOLD_F3:RW:16:16:=0x0000 ZQ_CALSTART_NORM_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_254	0x00000000 // ZQ_CS_NORM_THRESHOLD_F3:RW:16:16:=0x0000 ZQ_CALLATCH_HIGH_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_255	0x00000000 // ZQ_CALSTART_TIMEOUT_F3:RW:16:16:=0x0000 ZQ_CS_HIGH_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_256	0x00000000 // ZQ_CS_TIMEOUT_F3:RW:16:16:=0x0000 ZQ_CALLATCH_TIMEOUT_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_257	0x00000000 // ZQ_CALSTART_NORM_THRESHOLD_F4:RW:16:16:=0x0000 ZQ_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_258	0x00000000 // ZQ_CALLATCH_HIGH_THRESHOLD_F4:RW:16:16:=0x0000 ZQ_CALSTART_HIGH_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_259	0x00000000 // ZQ_CS_HIGH_THRESHOLD_F4:RW:16:16:=0x0000 ZQ_CS_NORM_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_260	0x00000000 // ZQ_CALLATCH_TIMEOUT_F4:RW:16:16:=0x0000 ZQ_CALSTART_TIMEOUT_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_261	0x00000000 // ZQ_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 ZQ_CS_TIMEOUT_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_262	0x0000EA03 // ZQINIT_F0:RW_D:8:12:=0x00ea RESERVED:RW:0:3:=0x03
#define LP3_DENALI_CTL_DATA_263	0x00150054 // ZQCS_F0:RW:16:12:=0x0015 ZQCL_F0:RW:0:12:=0x0054
#define LP3_DENALI_CTL_DATA_264	0x00000000 // TZQLAT_F0:RW:16:6:=0x00 TZQCAL_F0:RW:0:12:=0x0000
#define LP3_DENALI_CTL_DATA_265	0x00A801D3 // ZQCL_F1:RW:16:12:=0x00a8 ZQINIT_F1:RW_D:0:12:=0x01d3
#define LP3_DENALI_CTL_DATA_266	0x0000002A // TZQCAL_F1:RW:16:12:=0x0000 ZQCS_F1:RW:0:12:=0x002a
#define LP3_DENALI_CTL_DATA_267	0x00026E00 // ZQINIT_F2:RW_D:8:12:=0x026e TZQLAT_F1:RW:0:6:=0x00
#define LP3_DENALI_CTL_DATA_268	0x003800E0 // ZQCS_F2:RW:16:12:=0x0038 ZQCL_F2:RW:0:12:=0x00e0
#define LP3_DENALI_CTL_DATA_269	0x00000000 // TZQLAT_F2:RW:16:6:=0x00 TZQCAL_F2:RW:0:12:=0x0000
#define LP3_DENALI_CTL_DATA_270	0x015103A6 // ZQCL_F3:RW:16:12:=0x0151 ZQINIT_F3:RW_D:0:12:=0x03a6
#define LP3_DENALI_CTL_DATA_271	0x00000055 // TZQCAL_F3:RW:16:12:=0x0000 ZQCS_F3:RW:0:12:=0x0055
#define LP3_DENALI_CTL_DATA_272	0x0000EA00 // ZQINIT_F4:RW_D:8:12:=0x00ea TZQLAT_F3:RW:0:6:=0x00
#define LP3_DENALI_CTL_DATA_273	0x00150054 // ZQCS_F4:RW:16:12:=0x0015 ZQCL_F4:RW:0:12:=0x0054
#define LP3_DENALI_CTL_DATA_274	0x00000000 // ZQ_SW_REQ_START_LATCH_MAP:RW:24:2:=0x00 TZQLAT_F4:RW:16:6:=0x00 TZQCAL_F4:RW:0:12:=0x0000
#define LP3_DENALI_CTL_DATA_275	0x000C0000 // ZQRESET_F0:RW:16:12:=0x000c ZQ_REQ_PENDING:RD:8:1:=0x00 ZQ_REQ:WR:0:4:=0x00
#define LP3_DENALI_CTL_DATA_276	0x00200018 // ZQRESET_F2:RW:16:12:=0x0020 ZQRESET_F1:RW:0:12:=0x0018
#define LP3_DENALI_CTL_DATA_277	0x000C002F // ZQRESET_F4:RW:16:12:=0x000c ZQRESET_F3:RW:0:12:=0x002f
#define LP3_DENALI_CTL_DATA_278	0x01010100 // ZQ_CAL_LATCH_MAP_0:RW_D:24:2:=0x01 ZQ_CAL_START_MAP_0:RW_D:16:2:=0x01 ZQCS_ROTATE:RW:8:1:=0x01 NO_ZQ_INIT:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_279	0x01000202 // ROW_DIFF:RW:24:3:=0x01 BANK_DIFF:RW:16:2:=0x00 ZQ_CAL_LATCH_MAP_1:RW_D:8:2:=0x02 ZQ_CAL_START_MAP_1:RW_D:0:2:=0x02
#define LP3_DENALI_CTL_DATA_280	0x0A000002 // APREBIT:RW_D:24:4:=0x0a BANK_ADDR_INTLV_EN:RW:16:1:=0x00 BANK_START_BIT:RW:8:5:=0x00 COL_DIFF:RW:0:4:=0x02
#define LP3_DENALI_CTL_DATA_281	0x0101FFFF // RESERVED:RW:24:1:=0x01 ADDR_CMP_EN:RW:16:1:=0x01 COMMAND_AGE_COUNT:RW:8:8:=0xff AGE_COUNT:RW:0:8:=0xff
#define LP3_DENALI_CTL_DATA_282	0x01010101 // RW_SAME_EN:RW:24:1:=0x01 PRIORITY_EN:RW:16:1:=0x01 PLACEMENT_EN:RW:8:1:=0x01 BANK_SPLIT_EN:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_283	0x01010101 // DISABLE_RW_GROUP_W_BNK_CONFLICT:RW:24:2:=0x01 W2R_SPLIT_EN:RW:16:1:=0x01 CS_SAME_EN:RW:8:1:=0x01 RW_SAME_PAGE_EN:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_284	0x0000011B // INHIBIT_DRAM_CMD:RW:24:2:=0x00 DISABLE_RD_INTERLEAVE:RW:16:1:=0x00 SWAP_EN:RW:8:1:=0x01 NUM_Q_ENTRIES_ACT_DISABLE:RW:0:5:=0x1b
#define LP3_DENALI_CTL_DATA_285	0x01000003 // RESERVED:RW:24:4:=0x01 MEMDATA_RATIO_0:RW:16:3:=0x00 REDUC:RW:8:1:=0x00 CS_MAP:RW:0:2:=0x03
#define LP3_DENALI_CTL_DATA_286	0x00000000 // MEMDATA_RATIO_1:RW:24:3:=0x00 RESERVED:RW:16:4:=0x00 RESERVED:RW:8:4:=0x00 RESERVED:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_287	0x00000001 // RESERVED:RW:24:4:=0x00 RESERVED:RW:16:4:=0x00 RESERVED:RW:8:4:=0x00 RESERVED:RW:0:4:=0x01
#define LP3_DENALI_CTL_DATA_288	0x00000000 // CONTROLLER_BUSY:RD:24:1:=0x00 WR_ORDER_REQ:RW:16:2:=0x00 IN_ORDER_ACCEPT:RW:8:1:=0x00 Q_FULLNESS:RW:0:5:=0x00
#define LP3_DENALI_CTL_DATA_289	0x01000100 // RD_PREAMBLE_TRAINING_EN:RW:24:1:=0x01 PREAMBLE_SUPPORT:RW:16:2:=0x00 CTRLUPD_REQ_PER_AREF_EN:RW:8:1:=0x01 CTRLUPD_REQ:WR:0:1:=0x00
#define LP3_DENALI_CTL_DATA_290	0x00000000 // DFI_ERROR:RD:16:5:=0x00 RD_DBI_EN:RW:8:1:=0x00 WR_DBI_EN:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_291	0x00000000 // RESERVED:RW+:24:1:=0x00 DFI_ERROR_INFO:RD:0:20:=0x000000
#define LP3_DENALI_CTL_DATA_292	0x00000000 // INT_STATUS:RD:0:39:=0x00000000
#define LP3_DENALI_CTL_DATA_293	0x00000000 // INT_STATUS:RD:0:39:=0x00
#define LP3_DENALI_CTL_DATA_294	0x00000000 // INT_ACK:WR:0:38:=0x00000000
#define LP3_DENALI_CTL_DATA_295	0x00000000 // INT_ACK:WR:0:38:=0x00
#define LP3_DENALI_CTL_DATA_296	0x00000000 // INT_MASK:RW:0:39:=0x00000000
#define LP3_DENALI_CTL_DATA_297	0x00000000 // INT_MASK:RW:0:39:=0x00
#define LP3_DENALI_CTL_DATA_298	0x00000000 // OUT_OF_RANGE_ADDR:RD:0:34:=0x00000000
#define LP3_DENALI_CTL_DATA_299	0x00000000 // OUT_OF_RANGE_TYPE:RD:24:7:=0x00 OUT_OF_RANGE_LENGTH:RD:8:12:=0x0000 OUT_OF_RANGE_ADDR:RD:0:34:=0x00
#define LP3_DENALI_CTL_DATA_300	0x00000000 // OUT_OF_RANGE_SOURCE_ID:RD:0:19:=0x000000
#define LP3_DENALI_CTL_DATA_301	0x00000000 // BIST_EXP_DATA:RD:0:128:=0x00000000
#define LP3_DENALI_CTL_DATA_302	0x00000000 // BIST_EXP_DATA:RD:0:128:=0x00000000
#define LP3_DENALI_CTL_DATA_303	0x00000000 // BIST_EXP_DATA:RD:0:128:=0x00000000
#define LP3_DENALI_CTL_DATA_304	0x00000000 // BIST_EXP_DATA:RD:0:128:=0x00000000
#define LP3_DENALI_CTL_DATA_305	0x00000000 // BIST_FAIL_DATA:RD:0:128:=0x00000000
#define LP3_DENALI_CTL_DATA_306	0x00000000 // BIST_FAIL_DATA:RD:0:128:=0x00000000
#define LP3_DENALI_CTL_DATA_307	0x00000000 // BIST_FAIL_DATA:RD:0:128:=0x00000000
#define LP3_DENALI_CTL_DATA_308	0x00000000 // BIST_FAIL_DATA:RD:0:128:=0x00000000
#define LP3_DENALI_CTL_DATA_309	0x00000000 // BIST_FAIL_ADDR:RD:0:34:=0x00000000
#define LP3_DENALI_CTL_DATA_310	0x00000000 // BIST_FAIL_ADDR:RD:0:34:=0x00
#define LP3_DENALI_CTL_DATA_311	0x00000000 // PORT_CMD_ERROR_ADDR:RD:0:34:=0x00000000
#define LP3_DENALI_CTL_DATA_312	0x00000000 // PORT_CMD_ERROR_ID:RD:8:19:=0x000000 PORT_CMD_ERROR_ADDR:RD:0:34:=0x00
#define LP3_DENALI_CTL_DATA_313	0x02010100 // ODT_RD_MAP_CS1:RW:24:2:=0x02 ODT_WR_MAP_CS0:RW:16:2:=0x01 ODT_RD_MAP_CS0:RW:8:2:=0x01 PORT_CMD_ERROR_TYPE:RD:0:2:=0x00
#define LP3_DENALI_CTL_DATA_314	0x03020102 // TODTL_2CMD_F2:RW:24:8:=0x03 TODTL_2CMD_F1:RW:16:8:=0x02 TODTL_2CMD_F0:RW:8:8:=0x01 ODT_WR_MAP_CS1:RW:0:2:=0x02
#define LP3_DENALI_CTL_DATA_315	0x07070104 // TODTH_RD:RW:24:4:=0x07 TODTH_WR:RW:16:4:=0x07 TODTL_2CMD_F4:RW:8:8:=0x01 TODTL_2CMD_F3:RW:0:8:=0x04
#define LP3_DENALI_CTL_DATA_316	0x01010101 // ODT_EN_F3:RW:24:1:=0x01 ODT_EN_F2:RW:16:1:=0x01 ODT_EN_F1:RW:8:1:=0x01 ODT_EN_F0:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_317	0x02020101 // WR_TO_ODTH_F1:RW:24:6:=0x02 WR_TO_ODTH_F0:RW:16:6:=0x02 EN_ODT_ASSERT_EXCEPT_RD:RW:8:1:=0x01 ODT_EN_F4:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_318	0x05020403 // RD_TO_ODTH_F0:RW:24:6:=0x05 WR_TO_ODTH_F4:RW:16:6:=0x02 WR_TO_ODTH_F3:RW:8:6:=0x04 WR_TO_ODTH_F2:RW:0:6:=0x03
#define LP3_DENALI_CTL_DATA_319	0x050C0807 // RD_TO_ODTH_F4:RW:24:6:=0x05 RD_TO_ODTH_F3:RW:16:6:=0x0c RD_TO_ODTH_F2:RW:8:6:=0x08 RD_TO_ODTH_F1:RW:0:6:=0x07
#define LP3_DENALI_CTL_DATA_320	0x08080808 // RW2MRW_DLY_F3:RW_D:24:4:=0x08 RW2MRW_DLY_F2:RW_D:16:4:=0x08 RW2MRW_DLY_F1:RW_D:8:4:=0x08 RW2MRW_DLY_F0:RW_D:0:4:=0x08
#define LP3_DENALI_CTL_DATA_321	0x02020208 // W2R_DIFFCS_DLY_F0:RW_D:24:5:=0x02 R2W_DIFFCS_DLY_F0:RW_D:16:5:=0x02 R2R_DIFFCS_DLY_F0:RW_D:8:5:=0x02 RW2MRW_DLY_F4:RW_D:0:4:=0x08
#define LP3_DENALI_CTL_DATA_322	0x01020201 // W2R_DIFFCS_DLY_F1:RW_D:24:5:=0x01 R2W_DIFFCS_DLY_F1:RW_D:16:5:=0x02 R2R_DIFFCS_DLY_F1:RW_D:8:5:=0x02 W2W_DIFFCS_DLY_F0:RW_D:0:5:=0x01
#define LP3_DENALI_CTL_DATA_323	0x03030201 // W2R_DIFFCS_DLY_F2:RW_D:24:5:=0x03 R2W_DIFFCS_DLY_F2:RW_D:16:5:=0x03 R2R_DIFFCS_DLY_F2:RW_D:8:5:=0x02 W2W_DIFFCS_DLY_F1:RW_D:0:5:=0x01
#define LP3_DENALI_CTL_DATA_324	0x01030201 // W2R_DIFFCS_DLY_F3:RW_D:24:5:=0x01 R2W_DIFFCS_DLY_F3:RW_D:16:5:=0x03 R2R_DIFFCS_DLY_F3:RW_D:8:5:=0x02 W2W_DIFFCS_DLY_F2:RW_D:0:5:=0x01
#define LP3_DENALI_CTL_DATA_325	0x02020201 // W2R_DIFFCS_DLY_F4:RW_D:24:5:=0x02 R2W_DIFFCS_DLY_F4:RW_D:16:5:=0x02 R2R_DIFFCS_DLY_F4:RW_D:8:5:=0x02 W2W_DIFFCS_DLY_F3:RW_D:0:5:=0x01
#define LP3_DENALI_CTL_DATA_326	0x02020001 // R2W_SAMECS_DLY_F1:RW_D:24:5:=0x02 R2W_SAMECS_DLY_F0:RW_D:16:5:=0x02 R2R_SAMECS_DLY:RW:8:5:=0x00 W2W_DIFFCS_DLY_F4:RW_D:0:5:=0x01
#define LP3_DENALI_CTL_DATA_327	0x00020202 // W2R_SAMECS_DLY:RW:24:5:=0x00 R2W_SAMECS_DLY_F4:RW_D:16:5:=0x02 R2W_SAMECS_DLY_F3:RW_D:8:5:=0x02 R2W_SAMECS_DLY_F2:RW_D:0:5:=0x02
#define LP3_DENALI_CTL_DATA_328	0x03010200 // TDQSCK_MAX_F1:RW:24:4:=0x03 TDQSCK_MIN_F0:RW:16:2:=0x01 TDQSCK_MAX_F0:RW:8:4:=0x02 W2W_SAMECS_DLY:RW:0:5:=0x00
#define LP3_DENALI_CTL_DATA_329	0x06020402 // TDQSCK_MAX_F3:RW:24:4:=0x06 TDQSCK_MIN_F2:RW:16:2:=0x02 TDQSCK_MAX_F2:RW:8:4:=0x04 TDQSCK_MIN_F1:RW:0:2:=0x02
#define LP3_DENALI_CTL_DATA_330	0x00010203 // SW_LEVELING_MODE:RW:24:3:=0x00 TDQSCK_MIN_F4:RW:16:2:=0x01 TDQSCK_MAX_F4:RW:8:4:=0x02 TDQSCK_MIN_F3:RW:0:2:=0x03
#define LP3_DENALI_CTL_DATA_331	0x00000000 // SWLVL_OP_DONE:RD:24:1:=0x00 SWLVL_EXIT:WR:16:1:=0x00 SWLVL_START:WR:8:1:=0x00 SWLVL_LOAD:WR:0:1:=0x00
#define LP3_DENALI_CTL_DATA_332	0x00000000 // SWLVL_RESP_3:RD:24:1:=0x00 SWLVL_RESP_2:RD:16:1:=0x00 SWLVL_RESP_1:RD:8:1:=0x00 SWLVL_RESP_0:RD:0:1:=0x00
#define LP3_DENALI_CTL_DATA_333	0x0D000001 // WLDQSEN:RW:24:6:=0x0d WRLVL_CS:RW:16:1:=0x00 WRLVL_REQ:WR:8:1:=0x00 PHYUPD_APPEND_EN:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_334	0x00010028 // WRLVL_PERIODIC:RW:24:1:=0x00 DFI_PHY_WRLVL_MODE:RW:16:1:=0x01 WRLVL_EN:RW:8:1:=0x00 WLMRD:RW:0:6:=0x28
#define LP3_DENALI_CTL_DATA_335	0x00010000 // WRLVL_ROTATE:RW:24:1:=0x00 WRLVL_AREF_EN:RW:16:1:=0x01 WRLVL_RESP_MASK:RW:8:4:=0x00 WRLVL_ON_SREF_EXIT:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_336	0x00000003 // WRLVL_NORM_THRESHOLD_F0:RW:16:16:=0x0000 WRLVL_ERROR_STATUS:RD:8:2:=0x00 WRLVL_CS_MAP:RW:0:2:=0x03
#define LP3_DENALI_CTL_DATA_337	0x00000000 // WRLVL_TIMEOUT_F0:RW:16:16:=0x0000 WRLVL_HIGH_THRESHOLD_F0:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_338	0x00000000 // WRLVL_DFI_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 WRLVL_SW_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_339	0x00000000 // WRLVL_HIGH_THRESHOLD_F1:RW:16:16:=0x0000 WRLVL_NORM_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_340	0x00000000 // WRLVL_SW_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 WRLVL_TIMEOUT_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_341	0x00000000 // WRLVL_NORM_THRESHOLD_F2:RW:16:16:=0x0000 WRLVL_DFI_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_342	0x00000000 // WRLVL_TIMEOUT_F2:RW:16:16:=0x0000 WRLVL_HIGH_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_343	0x00000000 // WRLVL_DFI_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 WRLVL_SW_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_344	0x00000000 // WRLVL_HIGH_THRESHOLD_F3:RW:16:16:=0x0000 WRLVL_NORM_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_345	0x00000000 // WRLVL_SW_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 WRLVL_TIMEOUT_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_346	0x00000000 // WRLVL_NORM_THRESHOLD_F4:RW:16:16:=0x0000 WRLVL_DFI_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_347	0x00000000 // WRLVL_TIMEOUT_F4:RW:16:16:=0x0000 WRLVL_HIGH_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_348	0x00000000 // WRLVL_DFI_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 WRLVL_SW_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_349	0x00000000 // RDLVL_SEQ_EN:RW:24:4:=0x00 RDLVL_CS:RW:16:1:=0x00 RDLVL_GATE_REQ:WR:8:1:=0x00 RDLVL_REQ:WR:0:1:=0x00
#define LP3_DENALI_CTL_DATA_350	0x00010100 // RDLVL_PERIODIC:RW:24:1:=0x00 DFI_PHY_RDLVL_GATE_MODE:RW:16:1:=0x01 DFI_PHY_RDLVL_MODE:RW:8:1:=0x01 RDLVL_GATE_SEQ_EN:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_351	0x01000000 // RDLVL_AREF_EN:RW:24:1:=0x01 RDLVL_GATE_ON_SREF_EXIT:RW:16:1:=0x00 RDLVL_GATE_PERIODIC:RW:8:1:=0x00 RDLVL_ON_SREF_EXIT:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_352	0x00000001 // RDLVL_GATE_ROTATE:RW:24:1:=0x00 RDLVL_ROTATE:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RDLVL_GATE_AREF_EN:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_353	0x00000303 // RDLVL_NORM_THRESHOLD_F0:RW:16:16:=0x0000 RDLVL_GATE_CS_MAP:RW:8:2:=0x03 RDLVL_CS_MAP:RW:0:2:=0x03
#define LP3_DENALI_CTL_DATA_354	0x00000000 // RDLVL_TIMEOUT_F0:RW:16:16:=0x0000 RDLVL_HIGH_THRESHOLD_F0:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_355	0x00000000 // RDLVL_DFI_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 RDLVL_SW_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_356	0x00000000 // RDLVL_GATE_HIGH_THRESHOLD_F0:RW:16:16:=0x0000 RDLVL_GATE_NORM_THRESHOLD_F0:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_357	0x00000000 // RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 RDLVL_GATE_TIMEOUT_F0:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_358	0x00000000 // RDLVL_NORM_THRESHOLD_F1:RW:16:16:=0x0000 RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_359	0x00000000 // RDLVL_TIMEOUT_F1:RW:16:16:=0x0000 RDLVL_HIGH_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_360	0x00000000 // RDLVL_DFI_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 RDLVL_SW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_361	0x00000000 // RDLVL_GATE_HIGH_THRESHOLD_F1:RW:16:16:=0x0000 RDLVL_GATE_NORM_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_362	0x00000000 // RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 RDLVL_GATE_TIMEOUT_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_363	0x00000000 // RDLVL_NORM_THRESHOLD_F2:RW:16:16:=0x0000 RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_364	0x00000000 // RDLVL_TIMEOUT_F2:RW:16:16:=0x0000 RDLVL_HIGH_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_365	0x00000000 // RDLVL_DFI_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 RDLVL_SW_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_366	0x00000000 // RDLVL_GATE_HIGH_THRESHOLD_F2:RW:16:16:=0x0000 RDLVL_GATE_NORM_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_367	0x00000000 // RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 RDLVL_GATE_TIMEOUT_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_368	0x00000000 // RDLVL_NORM_THRESHOLD_F3:RW:16:16:=0x0000 RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_369	0x00000000 // RDLVL_TIMEOUT_F3:RW:16:16:=0x0000 RDLVL_HIGH_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_370	0x00000000 // RDLVL_DFI_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 RDLVL_SW_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_371	0x00000000 // RDLVL_GATE_HIGH_THRESHOLD_F3:RW:16:16:=0x0000 RDLVL_GATE_NORM_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_372	0x00000000 // RDLVL_GATE_SW_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 RDLVL_GATE_TIMEOUT_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_373	0x00000000 // RDLVL_NORM_THRESHOLD_F4:RW:16:16:=0x0000 RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_374	0x00000000 // RDLVL_TIMEOUT_F4:RW:16:16:=0x0000 RDLVL_HIGH_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_375	0x00000000 // RDLVL_DFI_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 RDLVL_SW_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_376	0x00000000 // RDLVL_GATE_HIGH_THRESHOLD_F4:RW:16:16:=0x0000 RDLVL_GATE_NORM_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_377	0x00000000 // RDLVL_GATE_SW_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 RDLVL_GATE_TIMEOUT_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_378	0x00000000 // CALVL_CS:RW:24:1:=0x00 CALVL_REQ:WR:16:1:=0x00 RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_379	0x000556AA // CALVL_PAT_0:RW:0:20:=0x0556aa
#define LP3_DENALI_CTL_DATA_380	0x000AAAAA // CALVL_BG_PAT_0:RW:0:20:=0x0aaaaa
#define LP3_DENALI_CTL_DATA_381	0x000AA955 // CALVL_PAT_1:RW:0:20:=0x0aa955
#define LP3_DENALI_CTL_DATA_382	0x00055555 // CALVL_BG_PAT_1:RW:0:20:=0x055555
#define LP3_DENALI_CTL_DATA_383	0x000B3133 // CALVL_PAT_2:RW:0:20:=0x0b3133
#define LP3_DENALI_CTL_DATA_384	0x0004CD33 // CALVL_BG_PAT_2:RW:0:20:=0x04cd33
#define LP3_DENALI_CTL_DATA_385	0x0004CECC // CALVL_PAT_3:RW:0:20:=0x04cecc
#define LP3_DENALI_CTL_DATA_386	0x000B32CC // RESERVED:RW:24:1:=0x00 CALVL_BG_PAT_3:RW:0:20:=0x0b32cc
#define LP3_DENALI_CTL_DATA_387	0x00010300 // CALVL_PERIODIC:RW:24:1:=0x00 DFI_PHY_CALVL_MODE:RW:16:1:=0x01 CALVL_SEQ_EN:RW:8:2:=0x03 RESERVED:RW:0:4:=0x00
#define LP3_DENALI_CTL_DATA_388	0x03000100 // CALVL_CS_MAP:RW:24:2:=0x03 CALVL_ROTATE:RW:16:1:=0x00 CALVL_AREF_EN:RW:8:1:=0x01 CALVL_ON_SREF_EXIT:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_389	0x00000000 // CALVL_HIGH_THRESHOLD_F0:RW:16:16:=0x0000 CALVL_NORM_THRESHOLD_F0:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_390	0x00000000 // CALVL_SW_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000 CALVL_TIMEOUT_F0:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_391	0x00000000 // CALVL_NORM_THRESHOLD_F1:RW:16:16:=0x0000 CALVL_DFI_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_392	0x00000000 // CALVL_TIMEOUT_F1:RW:16:16:=0x0000 CALVL_HIGH_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_393	0x00000000 // CALVL_DFI_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000 CALVL_SW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_394	0x00000000 // CALVL_HIGH_THRESHOLD_F2:RW:16:16:=0x0000 CALVL_NORM_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_395	0x00000000 // CALVL_SW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000 CALVL_TIMEOUT_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_396	0x00000000 // CALVL_NORM_THRESHOLD_F3:RW:16:16:=0x0000 CALVL_DFI_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_397	0x00000000 // CALVL_TIMEOUT_F3:RW:16:16:=0x0000 CALVL_HIGH_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_398	0x00000000 // CALVL_DFI_PROMOTE_THRESHOLD_F3:RW:16:16:=0x0000 CALVL_SW_PROMOTE_THRESHOLD_F3:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_399	0x00000000 // CALVL_HIGH_THRESHOLD_F4:RW:16:16:=0x0000 CALVL_NORM_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_400	0x00000000 // CALVL_SW_PROMOTE_THRESHOLD_F4:RW:16:16:=0x0000 CALVL_TIMEOUT_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_401	0x00000000 // AXI0_FIXED_PORT_PRIORITY_ENABLE:RW:24:1:=0x00 AXI0_ALL_STROBES_USED_ENABLE:RW:16:1:=0x00 CALVL_DFI_PROMOTE_THRESHOLD_F4:RW:0:16:=0x0000
#define LP3_DENALI_CTL_DATA_402	0x00000303 // AXI1_ALL_STROBES_USED_ENABLE:RW:24:1:=0x00 AXI0_FIFO_TYPE_REG:RW:16:2:=0x00 AXI0_W_PRIORITY:RW:8:4:=0x03 AXI0_R_PRIORITY:RW:0:4:=0x03
#define LP3_DENALI_CTL_DATA_403	0x00030300 // AXI1_FIFO_TYPE_REG:RW:24:2:=0x00 AXI1_W_PRIORITY:RW:16:4:=0x03 AXI1_R_PRIORITY:RW:8:4:=0x03 AXI1_FIXED_PORT_PRIORITY_ENABLE:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_404	0x03030000 // AXI2_W_PRIORITY:RW:24:4:=0x03 AXI2_R_PRIORITY:RW:16:4:=0x03 AXI2_FIXED_PORT_PRIORITY_ENABLE:RW:8:1:=0x00 AXI2_ALL_STROBES_USED_ENABLE:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_405	0x03000000 // AXI3_R_PRIORITY:RW:24:4:=0x03 AXI3_FIXED_PORT_PRIORITY_ENABLE:RW:16:1:=0x00 AXI3_ALL_STROBES_USED_ENABLE:RW:8:1:=0x00 AXI2_FIFO_TYPE_REG:RW:0:2:=0x00
#define LP3_DENALI_CTL_DATA_406	0x00000003 // AXI4_FIXED_PORT_PRIORITY_ENABLE:RW:24:1:=0x00 AXI4_ALL_STROBES_USED_ENABLE:RW:16:1:=0x00 AXI3_FIFO_TYPE_REG:RW:8:2:=0x00 AXI3_W_PRIORITY:RW:0:4:=0x03
#define LP3_DENALI_CTL_DATA_407	0x00000303 // AXI5_ALL_STROBES_USED_ENABLE:RW:24:1:=0x00 AXI4_FIFO_TYPE_REG:RW:16:2:=0x00 AXI4_W_PRIORITY:RW:8:4:=0x03 AXI4_R_PRIORITY:RW:0:4:=0x03
#define LP3_DENALI_CTL_DATA_408	0x00030300 // AXI5_FIFO_TYPE_REG:RW:24:2:=0x00 AXI5_W_PRIORITY:RW:16:4:=0x03 AXI5_R_PRIORITY:RW:8:4:=0x03 AXI5_FIXED_PORT_PRIORITY_ENABLE:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_409	0x0001210F // AXI0_CURRENT_BDW:RD:24:7:=0x00 AXI0_BDW_OVFLOW:RW:16:1:=0x01 AXI0_BDW:RW:8:7:=0x21 ARB_CMD_Q_THRESHOLD:RW:0:5:=0x0f
#define LP3_DENALI_CTL_DATA_410	0x21000121 // AXI2_BDW:RW:24:7:=0x21 AXI1_CURRENT_BDW:RD:16:7:=0x00 AXI1_BDW_OVFLOW:RW:8:1:=0x01 AXI1_BDW:RW:0:7:=0x21
#define LP3_DENALI_CTL_DATA_411	0x01210001 // AXI3_BDW_OVFLOW:RW:24:1:=0x01 AXI3_BDW:RW:16:7:=0x21 AXI2_CURRENT_BDW:RD:8:7:=0x00 AXI2_BDW_OVFLOW:RW:0:1:=0x01
#define LP3_DENALI_CTL_DATA_412	0x00012100 // AXI4_CURRENT_BDW:RD:24:7:=0x00 AXI4_BDW_OVFLOW:RW:16:1:=0x01 AXI4_BDW:RW:8:7:=0x21 AXI3_CURRENT_BDW:RD:0:7:=0x00
#define LP3_DENALI_CTL_DATA_413	0x00000121 // CKE_STATUS:RD:24:2:=0x00 AXI5_CURRENT_BDW:RD:16:7:=0x00 AXI5_BDW_OVFLOW:RW:8:1:=0x01 AXI5_BDW:RW:0:7:=0x21
#define LP3_DENALI_CTL_DATA_414	0x00000000 // DLL_RST_ADJ_DLY:RW:24:8:=0x00 DLL_RST_DELAY:RW:8:16:=0x0000 MEM_RST_VALID:RD:0:1:=0x00
#define LP3_DENALI_CTL_DATA_415	0x1C170000 // TDFI_PHY_RDLAT_F1:RW_D:24:7:=0x1c TDFI_PHY_RDLAT_F0:RW_D:16:7:=0x17 UPDATE_ERROR_STATUS:RD:8:7:=0x00 TDFI_PHY_WRLAT:RD:0:7:=0x00
#define LP3_DENALI_CTL_DATA_416	0x0017261F // TDFI_RDDATA_EN:RD:24:7:=0x00 TDFI_PHY_RDLAT_F4:RW_D:16:7:=0x17 TDFI_PHY_RDLAT_F3:RW_D:8:7:=0x26 TDFI_PHY_RDLAT_F2:RW_D:0:7:=0x1f
#define LP3_DENALI_CTL_DATA_417	0x070A0800 // TDFI_CTRLUPD_MAX_F0:RW:16:16:=0x070a TDFI_CTRLUPD_MIN:RW:8:4:=0x08 DRAM_CLK_DISABLE:RW:0:2:=0x00
#define LP3_DENALI_CTL_DATA_418	0x00000200 // TDFI_PHYUPD_TYPE0_F0:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_419	0x00000200 // TDFI_PHYUPD_TYPE1_F0:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_420	0x00000200 // TDFI_PHYUPD_TYPE2_F0:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_421	0x00000200 // TDFI_PHYUPD_TYPE3_F0:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_422	0x0000070A // TDFI_PHYUPD_RESP_F0:RW:0:16:=0x070a
#define LP3_DENALI_CTL_DATA_423	0x00004664 // TDFI_CTRLUPD_INTERVAL_F0:RW:0:32:=0x00004664
#define LP3_DENALI_CTL_DATA_424	0x0E260205 // TDFI_CTRLUPD_MAX_F1:RW:16:16:=0x0e26 WRLAT_ADJ_F0:RW:8:7:=0x02 RDLAT_ADJ_F0:RW:0:7:=0x05
#define LP3_DENALI_CTL_DATA_425	0x00000200 // TDFI_PHYUPD_TYPE0_F1:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_426	0x00000200 // TDFI_PHYUPD_TYPE1_F1:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_427	0x00000200 // TDFI_PHYUPD_TYPE2_F1:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_428	0x00000200 // TDFI_PHYUPD_TYPE3_F1:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_429	0x00000E26 // TDFI_PHYUPD_RESP_F1:RW:0:16:=0x0e26
#define LP3_DENALI_CTL_DATA_430	0x00008D7C // TDFI_CTRLUPD_INTERVAL_F1:RW:0:32:=0x00008d7c
#define LP3_DENALI_CTL_DATA_431	0x12E20305 // TDFI_CTRLUPD_MAX_F2:RW:16:16:=0x12e2 WRLAT_ADJ_F1:RW:8:7:=0x03 RDLAT_ADJ_F1:RW:0:7:=0x05
#define LP3_DENALI_CTL_DATA_432	0x00000200 // TDFI_PHYUPD_TYPE0_F2:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_433	0x00000200 // TDFI_PHYUPD_TYPE1_F2:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_434	0x00000200 // TDFI_PHYUPD_TYPE2_F2:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_435	0x00000200 // TDFI_PHYUPD_TYPE3_F2:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_436	0x000012E2 // TDFI_PHYUPD_RESP_F2:RW:0:16:=0x12e2
#define LP3_DENALI_CTL_DATA_437	0x0000BCD4 // TDFI_CTRLUPD_INTERVAL_F2:RW:0:32:=0x0000bcd4
#define LP3_DENALI_CTL_DATA_438	0x1C620506 // TDFI_CTRLUPD_MAX_F3:RW:16:16:=0x1c62 WRLAT_ADJ_F2:RW:8:7:=0x05 RDLAT_ADJ_F2:RW:0:7:=0x06
#define LP3_DENALI_CTL_DATA_439	0x00000200 // TDFI_PHYUPD_TYPE0_F3:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_440	0x00000200 // TDFI_PHYUPD_TYPE1_F3:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_441	0x00000200 // TDFI_PHYUPD_TYPE2_F3:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_442	0x00000200 // TDFI_PHYUPD_TYPE3_F3:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_443	0x00001C62 // TDFI_PHYUPD_RESP_F3:RW:0:16:=0x1c62
#define LP3_DENALI_CTL_DATA_444	0x00011BD4 // TDFI_CTRLUPD_INTERVAL_F3:RW:0:32:=0x00011bd4
#define LP3_DENALI_CTL_DATA_445	0x070A0708 // TDFI_CTRLUPD_MAX_F4:RW:16:16:=0x070a WRLAT_ADJ_F3:RW:8:7:=0x07 RDLAT_ADJ_F3:RW:0:7:=0x08
#define LP3_DENALI_CTL_DATA_446	0x00000200 // TDFI_PHYUPD_TYPE0_F4:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_447	0x00000200 // TDFI_PHYUPD_TYPE1_F4:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_448	0x00000200 // TDFI_PHYUPD_TYPE2_F4:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_449	0x00000200 // TDFI_PHYUPD_TYPE3_F4:RW:0:32:=0x00000200
#define LP3_DENALI_CTL_DATA_450	0x0000070A // TDFI_PHYUPD_RESP_F4:RW:0:16:=0x070a
#define LP3_DENALI_CTL_DATA_451	0x00004664 // TDFI_CTRLUPD_INTERVAL_F4:RW:0:32:=0x00004664
#define LP3_DENALI_CTL_DATA_452	0x02020205 // TDFI_CTRL_DELAY_F1:RW_D:24:4:=0x02 TDFI_CTRL_DELAY_F0:RW_D:16:4:=0x02 WRLAT_ADJ_F4:RW:8:7:=0x02 RDLAT_ADJ_F4:RW:0:7:=0x05
#define LP3_DENALI_CTL_DATA_453	0x02020202 // TDFI_DRAM_CLK_DISABLE:RW:24:4:=0x02 TDFI_CTRL_DELAY_F4:RW_D:16:4:=0x02 TDFI_CTRL_DELAY_F3:RW_D:8:4:=0x02 TDFI_CTRL_DELAY_F2:RW_D:0:4:=0x02
#define LP3_DENALI_CTL_DATA_454	0x00180303 // TDFI_WRLVL_WW:RW:16:10:=0x0018 TDFI_WRLVL_EN:RW:8:8:=0x03 TDFI_DRAM_CLK_ENABLE:RW:0:4:=0x03
#define LP3_DENALI_CTL_DATA_455	0x00000000 // TDFI_WRLVL_RESP:RW:0:32:=0x00000000
#define LP3_DENALI_CTL_DATA_456	0x00000000 // TDFI_WRLVL_MAX:RW:0:32:=0x00000000
#define LP3_DENALI_CTL_DATA_457	0x00001403 // TDFI_RDLVL_RR:RW:8:10:=0x0014 TDFI_RDLVL_EN:RW:0:8:=0x03
#define LP3_DENALI_CTL_DATA_458	0x00000000 // TDFI_RDLVL_RESP:RW:0:32:=0x00000000
#define LP3_DENALI_CTL_DATA_459	0x00000000 // RDLVL_GATE_EN:RW:16:1:=0x00 RDLVL_EN:RW:8:1:=0x00 RDLVL_RESP_MASK:RW:0:8:=0x00
#define LP3_DENALI_CTL_DATA_460	0x00000000 // TDFI_RDLVL_MAX:RW:0:32:=0x00000000
#define LP3_DENALI_CTL_DATA_461	0x00030000 // TDFI_CALVL_EN:RW:16:8:=0x03 RDLVL_GATE_ERROR_STATUS:RD:8:2:=0x00 RDLVL_ERROR_STATUS:RD:0:2:=0x00
#define LP3_DENALI_CTL_DATA_462	0x0008001A // TDFI_CALVL_CAPTURE_F0:RW:16:10:=0x0008 TDFI_CALVL_CC_F0:RW:0:10:=0x001a
#define LP3_DENALI_CTL_DATA_463	0x000B001D // TDFI_CALVL_CAPTURE_F1:RW:16:10:=0x000b TDFI_CALVL_CC_F1:RW:0:10:=0x001d
#define LP3_DENALI_CTL_DATA_464	0x000C001E // TDFI_CALVL_CAPTURE_F2:RW:16:10:=0x000c TDFI_CALVL_CC_F2:RW:0:10:=0x001e
#define LP3_DENALI_CTL_DATA_465	0x000F0021 // TDFI_CALVL_CAPTURE_F3:RW:16:10:=0x000f TDFI_CALVL_CC_F3:RW:0:10:=0x0021
#define LP3_DENALI_CTL_DATA_466	0x0008001A // TDFI_CALVL_CAPTURE_F4:RW:16:10:=0x0008 TDFI_CALVL_CC_F4:RW:0:10:=0x001a
#define LP3_DENALI_CTL_DATA_467	0x00000000 // TDFI_CALVL_RESP:RW:0:32:=0x00000000
#define LP3_DENALI_CTL_DATA_468	0x00000000 // TDFI_CALVL_MAX:RW:0:32:=0x00000000
#define LP3_DENALI_CTL_DATA_469	0x01000000 // TDFI_PHY_WRDATA:RW:24:3:=0x01 CALVL_ERROR_STATUS:RD:16:4:=0x00 CALVL_EN:RW:8:1:=0x00 CALVL_RESP_MASK:RW:0:1:=0x00
#define LP3_DENALI_CTL_DATA_470	0x02030101 // TDFI_WRCSLAT_F1:RW:24:7:=0x02 TDFI_RDCSLAT_F1:RW:16:7:=0x03 TDFI_WRCSLAT_F0:RW:8:7:=0x01 TDFI_RDCSLAT_F0:RW:0:7:=0x01
#define LP3_DENALI_CTL_DATA_471	0x02090005 // TDFI_WRCSLAT_F3:RW:24:7:=0x02 TDFI_RDCSLAT_F3:RW:16:7:=0x09 TDFI_WRCSLAT_F2:RW:8:7:=0x00 TDFI_RDCSLAT_F2:RW:0:7:=0x05
#define LP3_DENALI_CTL_DATA_472	0x01050101 // EN_1T_TIMING:RW:24:1:=0x01 TDFI_WRDATA_DELAY:RW:16:8:=0x05 TDFI_WRCSLAT_F4:RW:8:7:=0x01 TDFI_RDCSLAT_F4:RW:0:7:=0x01
#define LP3_DENALI_CTL_DATA_473	0x01010001 // RESERVED:RW_D:24:3:=0x01 MULTI_CHANNEL_ZQ_CAL_MASTER:RW_D:16:1:=0x01 BL_ON_FLY_ENABLE:RW_D:8:1:=0x00 DISABLE_MEMORY_MASKED_WRITE:RW_D:0:1:=0x01
#define LP3_DENALI_CTL_DATA_474	0x01010101 // RESERVED:RW_D:24:3:=0x01 RESERVED:RW_D:16:3:=0x01 RESERVED:RW_D:8:3:=0x01 RESERVED:RW_D:0:3:=0x01
#define LP3_DENALI_CTL_DATA_475	0x00010001 // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x01 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:3:=0x01
#define LP3_DENALI_CTL_DATA_476	0x01010001 // RESERVED:RW_D:24:4:=0x01 RESERVED:RW_D:16:4:=0x01 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x01
#define LP3_DENALI_CTL_DATA_477	0x02000100 // RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x01 RESERVED:RW_D:0:4:=0x00
#define LP3_DENALI_CTL_DATA_478	0x00000100 // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x01 RESERVED:RW_D:0:4:=0x00
#define LP3_DENALI_CTL_DATA_479	0x02000201 // RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x01
#define LP3_DENALI_CTL_DATA_480	0x00000000 // RESERVED:RW_D:0:4:=0x00
    //}}}
#endif
#endif
